Michael Orshansky

	2009
35		Michael Orshansky, Wei-Shen Wang: Statistical analysis of circuit timing using majorization. Commun. ACM 52(8): 95-100 (2009)
	2008
34		Shayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky: Electrically driven optical proximity correction based on linear programming. ICCAD 2008: 473-479
33		Bin Zhang, Michael Orshansky: Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. ISQED 2008: 774-779
32		Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet Roychowdhury, Douglas L. Jones, Jan M. Rabaey: The Search for Alternative Computational Paradigms. IEEE Design & Test of Computers 25(4): 334-343 (2008)
	2007
31		Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham: Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI 2007: 61-66
30		Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan: Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153
29		Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky: Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies CoRR abs/cs/0703102: (2007)
28		Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan: A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1790-1802 (2007)
27		Wei-Shen Wang, Michael Orshansky: Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. J. Low Power Electronics 3(1): 1-12 (2007)
26		Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky: Architecting a reliable CMP switch architecture. TACO 4(1): (2007)
	2006
25		Joonsoo Kim, Michael Orshansky: Towards formal probabilistic power-performance design space exploration. ACM Great Lakes Symposium on VLSI 2006: 229-234
24		Murari Mani, Mahesh Sharma, Michael Orshansky: Application of fast SOCP based statistical sizing in the microprocessor design flow. ACM Great Lakes Symposium on VLSI 2006: 372-375
23		Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky: Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. DAC 2006: 161-166
22		Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky: Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. DAC 2006: 522-527
21		Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky: BulletProof: a defect-tolerant CMP switch architecture. HPCA 2006: 5-16
20		Murari Mani, Ashish Kumar Singh, Michael Orshansky: Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. ICCAD 2006: 19-26
19		Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan: An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236
18		Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky: Analytical modeling of SRAM dynamic stability. ICCAD 2006: 315-322
17		Wei-Shen Wang, Michael Orshansky: Robust estimation of parametric yield under limited descriptions of uncertainty. ICCAD 2006: 884-890
16		Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar: Tutorial II: Variability and Its Impact on Design. ISQED 2006: 5
15		Bin Zhang, Wei-Shen Wang, Michael Orshansky: FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. ISQED 2006: 755-760
14		Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang: Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips. SAC 2006: 1645-1649
13		Wei-Shen Wang, Michael Orshansky: Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2976-2988 (2006)
12		Wei-Shen Wang, Michael Liu, Michael Orshansky: Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. J. Low Power Electronics 2(1): 1-7 (2006)
	2005
11		Murari Mani, Anirudh Devgan, Michael Orshansky: An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC 2005: 309-314
10		Ashish Kumar Singh, Murari Mani, Michael Orshansky: Statistical technology mapping for parametric yield. ICCAD 2005: 511-518
	2004
9		Michael Orshansky, Arnab Bandyopadhyay: Fast statistical timing analysis handling arbitrary delay correlations. DAC 2004: 337-342
8		Murari Mani, Michael Orshansky: A New Statistical Optimization Algorithm for Gate Sizing. ICCD 2004: 272-277
7		Michael Liu, Wei-Shen Wang, Michael Orshansky: Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. ISLPED 2004: 2-7
	2003
6		David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer: Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ISLPED 2003: 158-163
	2002
5		Michael Orshansky, Kurt Keutzer: A general probabilistic framework for worst case timing analysis. DAC 2002: 556-561
4		Kurt Keutzer, Michael Orshansky: From blind certainty to informed uncertainty. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 37-41
3		Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 544-553 (2002)
	2000
2		Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu: Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD 2000: 62-67
	1998
1		Michael Orshansky, James C. Chen, Chenming Hu: A Statistical Performance Simulation Methodology for VLSI Circuits. DAC 1998: 402-407

Coauthor Index

1	Jacob A. Abraham	[31]
2	Ari Arapostathis	[18]
3	Todd M. Austin	[21] [26]
4	Adnan Aziz	[29]
5	Arnab Bandyopadhyay	[9]
6	Shayak Banerjee	[34]
7	Valeria Bertacco	[21] [26]
8	Jason A. Blome	[21] [26]
9	Keith A. Bowman	[16]
10	Martine Ceberio	[14]
11	James C. Chen	[1]
12	Pinhong Chen	[2] [3]
13	David G. Chinnery	[6]
14	Kypros Constantinides	[21] [26]
15	Abhijit Davare	[6]
16	Anirudh Devgan	[11] [28]
17	Praveen Elakkumanan	[34]
18	Chenming Hu	[1] [2] [3]
19	Douglas L. Jones	[32]
20	Vijay Kiran Kalyanam	[31]
21	Kurt Keutzer	[2] [3] [4] [5] [6]
22	Joonsoo Kim	[25]
23	Vladik Kreinovich	[23]
24	Lars Liebmann	[34]
25	Michael Liu	[7] [12]
26	Scott A. Mahlke	[21] [26]
27	Murari Mani	[8] [10] [11] [20] [22] [24] [28]
28	Radu Marculescu	[32]
29	Linda S. Milor (Linda Milor)	[2] [3]
30	Subhasish Mitra	[32]
31	Gi-Joon Nam	[19]
32	Sani R. Nassif	[18] [19] [30] [31]
33	David Nguyen	[6]
34	David Z. Pan (David Zhigang Pan)	[19] [30]
35	Stephen Plaza	[21] [26]
36	Ruchir Puri	[22]
37	Jan M. Rabaey	[32]
38	Anand Ramalingam	[19] [30]
39	Jaijeet Roychowdhury	[32]
40	Sachin S. Sapatnekar	[16]
41	Naresh R. Shanbhag	[32]
42	Mahesh Sharma	[24]
43	Ashish Kumar Singh	[10] [19] [20] [22] [29] [30]
44	Rajeshwary Tayade	[31]
45	Brandon Thompson	[6]
46	Gustavo de Veciana	[32]
47	Sriram Vishwanath	[29]
48	Wei-Shen Wang	[7] [12] [13] [14] [15] [17] [23] [27] [35]
49	Gang Xiang	[14]
50	Yaping Zhan	[28]
51	Bin Zhang	[15] [18] [21] [26] [33]

Colors in the list of coauthors