David Z. Pan

David Zhigang Pan

	2009
85		Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen, David Z. Pan: O-Router: an optical routing framework for low power on-chip silicon nano-photonic integration. DAC 2009: 264-269
84		Ashutosh Chakraborty, Anurag Kumar, David Z. Pan: RegPlace: a high quality open-source placement framework for structured ASICs. DAC 2009: 442-447
83		Kun Yuan, Katrina Lu, David Z. Pan: Double patterning lithography friendly detailed routing with redundant via consideration. DAC 2009: 63-66
82		Wooyoung Jang, David Z. Pan: An SDRAM-aware router for Networks-on-Chip. DAC 2009: 800-805
81		Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan: Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE 2009: 296-299
80		Kun Yuan, Jae-Seok Yang, David Z. Pan: Double patterning layout decomposition for simultaneous conflict and stitch minimization. ISPD 2009: 107-114
79		Ashutosh Chakraborty, David Z. Pan: On stress aware active area sizing, gate sizing, and repeater insertion. ISPD 2009: 35-42
78		Duo Ding, David Z. Pan: OIL: a nano-photonics optical interconnect library for a new photonic networks-on-chip architecture. SLIP 2009: 11-18
77		Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan: BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability. ACM Trans. Design Autom. Electr. Syst. 14(2): (2009)
	2008
76		David Z. Pan, Gi-Joon Nam: Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008 ACM 2008
75		David Z. Pan, Minsik Cho: Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond. ASP-DAC 2008: 220-225
74		Anand Rajaram, David Z. Pan: MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. ASP-DAC 2008: 250-257
73		Tao Luo, David Z. Pan: DPlace2.0: A stable and efficient analytical placement based on diffusion. ASP-DAC 2008: 346-351
72		Tao Luo, David Newmark, David Z. Pan: Total power optimization combining placement, sizing and multi-Vt through slack distribution management. ASP-DAC 2008: 352-357
71		Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan: ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. DAC 2008: 504-509
70		Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan: An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC 2008: 702-707
69		Anand Rajaram, David Z. Pan: Robust chip-level clock tree synthesis for SOC designs. DAC 2008: 720-723
68		Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan: Latch Modeling for Statistical Timing Analysis. DATE 2008: 1136-1141
67		Ashutosh Chakraborty, Sean X. Shi, David Z. Pan: Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices. DATE 2008: 849-855
66		Tao Luo, David A. Papa, Zhuo Li, Chin-Ngai Sze, Charles J. Alpert, David Z. Pan: Pyramids: an efficient computational geometry-based approach for timing-driven placement. ICCAD 2008: 204-211
65		Wooyoung Jang, Duo Ding, David Z. Pan: A voltage-frequency island aware energy optimization framework for networks-on-chip. ICCAD 2008: 264-269
64		Jae-Seok Yang, David Z. Pan: Overlay aware interconnect and timing variation modeling for double patterning technology. ICCAD 2008: 488-493
63		Minsik Cho, Yongchan Ban, David Z. Pan: Double patterning technology friendly detailed routing. ICCAD 2008: 506-511
62		David Z. Pan, Stephen Renwick, Vivek Singh, Judy Huckabay: Nanolithography and CAD challenges for 32nm/22nm and beyond. ICCAD 2008: 6
61		Minsik Cho, David Z. Pan: A high-performance droplet router for digital microfluidic biochips. ISPD 2008: 200-206
60		Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-density driven placement for cmp variation and routability. ISPD 2008: 31-38
59		David Z. Pan: Synergistic modeling and optimization for nanometer IC design/manufacturing integration. SBCCI 2008: 2
58		David Z. Pan: Lithography friendly routing: from construct-by-correction to correct-by-construction. SBCCI 2008: 6
57		Minsik Cho, David Z. Pan: Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs. IEEE Trans. VLSI Syst. 16(12): 1713-1717 (2008)
56		Minsik Cho, David Z. Pan: A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1714-1724 (2008)
55		David Z. Pan, Gi-Joon Nam: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2105-2106 (2008)
54		Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2145-2155 (2008)
53		Patrick H. Madden, David Z. Pan: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 608-609 (2008)
52		Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: Track Routing and Optimization for Yield. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 872-882 (2008)
	2007
51		Patrick H. Madden, David Z. Pan: Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007 ACM 2007
50		Haoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia: Hippocrates: First-Do-No-Harm Detailed Placement. ASP-DAC 2007: 141-146
49		Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan: Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC 2007: 148-153
48		Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: TROY: Track Router with Yield-driven Wire Planning. DAC 2007: 55-58
47		Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan: BoxRouter 2.0: architecture and implementation of a hybrid and robust global router. ICCAD 2007: 503-508
46		Peng Yu, David Z. Pan: TIP-OPC: a new topological invariant paradigm for pixel based optical proximity correction. ICCAD 2007: 847-853
45		Peng Yu, David Z. Pan: A novel intensity based optical proximity correction algorithm with speedup in lithography simulation. ICCAD 2007: 854-859
44		Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden: ISPD placement contest updates and ISPD 2007 global routing contest. ISPD 2007: 167
43		Anand Ramalingam, Giri Devarayanadurg, David Z. Pan: Accurate power grid analysis with behavioral transistor network modeling. ISPD 2007: 43-50
42		Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan: Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ISQED 2007: 398-403
41		Minsik Cho, David Z. Pan: BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2130-2143 (2007)
40		Haoxing Ren, David Z. Pan, Charles J. Alpert, Paul G. Villarrubia, Gi-Joon Nam: Diffusion-Based Placement Migration With Application on Legalization. IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2158-2172 (2007)
39		Anand Ramalingam, Anirudh Devgan, David Z. Pan: Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce. J. Low Power Electronics 3(1): 28-35 (2007)
	2006
38		Sean X. Shi, David Z. Pan: Wire sizing with scattering effect for nanoscale interconnection. ASP-DAC 2006: 503-508
37		Anand Ramalingam, Sreekumar V. Kodakara, Anirudh Devgan, David Z. Pan: Robust analytical gate delay modeling for low voltage circuits. ASP-DAC 2006: 61-66
36		Minsik Cho, Hongjoong Shin, David Z. Pan: Fast substrate noise-aware floorplanning with preference directed graph for mixed-signal SOCs. ASP-DAC 2006: 765-770
35		Tao Luo, David Newmark, David Z. Pan: A new LP based incremental timing driven placement for high performance designs. DAC 2006: 1115-1120
34		Minsik Cho, David Z. Pan: BoxRouter: a new global router based on box expansion and progressive ILP. DAC 2006: 373-378
33		Peng Yu, Sean X. Shi, David Z. Pan: Process variation aware OPC with variational lithography modeling. DAC 2006: 785-790
32		Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan: An accurate sparse matrix based framework for statistical static timing analysis. ICCAD 2006: 231-236
31		Sean X. Shi, Peng Yu, David Z. Pan: A unified non-rectangular device and circuit simulation model for timing and power. ICCAD 2006: 423-428
30		Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri: Wire density driven global routing for CMP variation and timing. ICCAD 2006: 487-492
29		Avijit Dutta, David Z. Pan: Partial Functional Manipulation Based Wirelength Minimization. ICCD 2006
28		Anand Rajaram, David Z. Pan: Variation tolerant buffered clock network synthesis with cross links. ISPD 2006: 157-164
27		Andrew Havlir, David Z. Pan: Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. ISQED 2006: 171-178
26		Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif: Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity. ISQED 2006: 644-649
25		Anand Rajaram, David Z. Pan: Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. ISQED 2006: 79-84
24		Minsik Cho, David Z. Pan: PEAKASO: Peak-Temperature Aware Scan-Vector Optimization. VTS 2006: 52-57
	2005
23		Anand Ramalingam, Bin Zhang, Anirudh Devgan, David Z. Pan: Sleep transistor sizing using timing criticality and temporal currents. ASP-DAC 2005: 1094-1097
22		Gang Xu, Ruiqi Tian, David Z. Pan, Martin D. F. Wong: CMP aware shuttle mask floorplanning. ASP-DAC 2005: 1111-1114
21		Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong: Redundant-via enhanced maze routing for yield improvement. ASP-DAC 2005: 1148-1151
20		Joydeep Mitra, Peng Yu, David Zhigang Pan: RADAR: RET-aware detailed routing using fast lithography simulations. DAC 2005: 369-372
19		Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia: Diffusion-based placement migration. DAC 2005: 515-520
18		Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan: Computational geometry based placement migration. ICCAD 2005: 41-47
17		Minsik Cho, Suhail Ahmed, David Z. Pan: TACO: temperature aware clock-tree optimization. ICCAD 2005: 582-587
16		Anand Rajaram, David Z. Pan, Jiang Hu: Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD 2005: 55-62
15		Haoxing Ren, David Zhigang Pan, David S. Kung: Sensitivity guided net weighting for placement-driven synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 711-721 (2005)
	2004
14		Haoxing Ren, David Zhigang Pan, Paul Villarrubia: True crosstalk aware incremental placement with noise map. ICCAD 2004: 402-409
13		Haoxing Ren, David Zhigang Pan, David S. Kung: Sensitivity guided net weighting for placement driven synthesis. ISPD 2004: 10-17
	2003
12		Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793
11		Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan: Multilevel global placement with congestion control. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 395-409 (2003)
	2002
10		Chin-Chih Chang, Jason Cong, David Zhigang Pan: Physical hierarchy generation with routing congestion control. ISPD 2002: 36-41
9		Jason Cong, David Zhigang Pan: Wire width planning for interconnect performance optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 319-329 (2002)
	2001
8		Jason Cong, David Zhigang Pan, Prasanna V. Srinivas: Improved crosstalk modeling for noise constrained interconnect optimization. ASP-DAC 2001: 373-378
7		Jason Cong, David Zhigang Pan: Interconnect performance estimation models for design planning. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 739-752 (2001)
6		Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1164-1169 (2001)
	1999
5		Jason Cong, David Zhigang Pan: Interconnect Delay Estimation Models for Synthesis and Design Planning. ASP-DAC 1999: 97-100
4		Jason Cong, David Zhigang Pan: Interconnect Estimation and Dlanning for Deep Submicron Designs. DAC 1999: 507-510
3		Jason Cong, Tianming Kong, David Zhigang Pan: Buffer block planning for interconnect-driven floorplanning. ICCAD 1999: 358-363
	1997
2		Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo: Interconnect design for deep submicron ICs. ICCAD 1997: 478-485
1		Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan: Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633

Coauthor Index

1	Suhail Ahmed	[17]
2	Charles J. Alpert	[18] [19] [40] [50] [66]
3	Yongchan Ban	[63] [71]
4	Ashutosh Chakraborty	[67] [70] [79] [81] [84]
5	Chin-Chih Chang	[10] [11]
6	Yao-Wen Chang	[54] [60]
7	Jian Chen	[42]
8	Ray T. Chen	[85]
9	Tung-Chieh Chen	[54] [60] [70]
10	Minsik Cho	[17] [24] [30] [34] [36] [41] [47] [48] [52] [54] [56] [57] [60] [61] [63] [71] [75] [77]
11	John M. Cohn	[12]
12	Jason Cong	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
13	Giri Devarayanadurg	[43]
14	Anirudh Devgan	[23] [37] [39]
15	Duo Ding	[65] [78] [85]
16	Avijit Dutta	[29]
17	Gokul Ganesan	[81]
18	Andrew Havlir	[27]
19	Lei He	[1] [2] [6]
20	Jiang Hu	[16]
21	Haiyu Huang	[85]
22	Li-Da Huang	[21]
23	Judy Huckabay	[62]
24	Wooyoung Jang	[65] [82]
25	Kei-Yong Khoo	[2]
26	Sreekumar V. Kodakara	[37]
27	Cheng-Kok Koh	[1] [2] [6]
28	Tianming Kong	[3]
29	Sarvesh H. Kulkarni	[12]
30	Anurag Kumar	[84]
31	David S. Kung	[12] [13] [15]
32	Zhuo Li	[66]
33	Frank Liu	[26]
34	Katrina Lu	[47] [77] [83]
35	Tao Luo	[18] [35] [66] [72] [73]
36	Patrick H. Madden	[44] [51] [53]
37	Joydeep Mitra	[20]
38	Gi-Joon Nam	[32] [40] [44] [50] [55] [76]
39	Sani R. Nassif	[26] [32] [49]
40	David Newmark	[35] [72]
41	Michael Orshansky	[32] [49]
42	David A. Papa	[66]
43	Ruchir Puri	[12] [30] [48] [52]
44	Anand Rajaram	[16] [25] [28] [42] [69] [74] [81]
45	Anand Ramalingam	[23] [26] [32] [37] [39] [43] [49] [68]
46	Haoxing Ren	[13] [14] [15] [18] [19] [40] [50]
47	Stephen Renwick	[62]
48	Ninghy Shi	[42]
49	Sean X. Shi	[31] [33] [38] [67] [68]
50	Hongjoong Shin	[36]
51	Ashish Kumar Singh	[32] [49]
52	Vivek Singh	[62]
53	Prasanna V. Srinivas	[8]
54	Ashish Srivastava	[12]
55	Leon Stok	[12]
56	Dennis Sylvester	[12]
57	Chin-Ngai Sze	[66]
58	Ruiqi Tian	[22]
59	Paul G. Villarrubia (Paul Villarrubia)	[14] [19] [40] [50]
60	Daifeng Wang	[68]
61	Martin D. F. Wong (D. F. Wong)	[21] [22]
62	Hua Xiang	[30] [48] [52]
63	Gang Xu	[21] [22]
64	Jae-Seok Yang	[64] [80]
65	Joon-Sung Yang	[42]
66	Mehmet Can Yildiz	[44]
67	Peng Yu	[20] [31] [33] [45] [46]
68	Kun Yuan	[47] [71] [77] [80] [83]
69	Xin Yuan	[11]
70	Bin Zhang	[23]
71	Yilin Zhang	[85]

Colors in the list of coauthors