Ivan Miro Panades

	2008
4		Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, Alain Greiner: Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture. NOCS 2008: 139-148
3		Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades: Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. IEEE Design & Test of Computers 25(6): 572-580 (2008)
	2007
2		Abbas Sheibanyrad, Ivan Miro Panades, Alain Greiner: Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture. DATE 2007: 1090-1095
1		Ivan Miro Panades, Alain Greiner: Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures. NOCS 2007: 83-94

Coauthor Index

1	Fabien Clermidy	[4]
2	Alain Greiner	[1] [2] [3] [4]
3	Abbas Sheibanyrad	[2] [3]
4	Pascal Vivet	[4]