Rajendran Panda

	2009
58		Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal: Characterization of sequential cells for constraint sensitivities. ISQED 2009: 74-79
	2008
57		Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda: Characterization of Standard Cells for Intra-Cell Mismatch Variations. ISQED 2008: 213-219
56		Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu: Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED 2008: 627-632
55		Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman Solovyev, Jacob A. Abraham: A timing methodology considering within-die clock skew variations. SoCC 2008: 351-356
	2007
54		Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan: On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. DAC 2007: 162-167
53		Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu: Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD 2007: 627-631
52		Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao: A novel technique for incremental analysis of on-chip power distribution networks. ICCAD 2007: 817-823
51		Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang: Stochastic Power Grid Analysis Considering Process Variations CoRR abs/0710.4649: (2007)
	2006
50		Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda: Stochastic variational analysis of large power grids considering intra-die correlations. DAC 2006: 211-216
49		Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu: A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. DAC 2006: 217-222
48		Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Optimal placement of power-supply pads and pins. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 144-154 (2006)
47		Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda: Impact of stress-induced backflow on full-chip electromigration risk assessment. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1038-1046 (2006)
	2005
46		Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang: Stochastic Power Grid Analysis Considering Process Variations. DATE 2005: 964-969
45		Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh: Pessimism reduction in crosstalk noise aware STA. ICCAD 2005: 954-961
	2004
44		Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Optimal placement of power supply pads and pins. DAC 2004: 165-170
43		Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: A stochastic approach To power grid analysis. DAC 2004: 171-176
42		Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer: False-Noise Analysis for Domino Circuits. DATE 2004: 784-789
41		Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda: Delay noise pessimism reduction by logic correlations. ICCAD 2004: 160-167
40		Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda: A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. ISQED 2004: 232-237
39		Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Postroute gate sizing for crosstalk noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1670-1677 (2004)
38		Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda: Crosstalk noise control in an SoC physical design flow. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 488-497 (2004)
	2003
37		Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957
36		D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel: SOI Transistor Model for Fast Transient Simulation. ICCAD 2003: 120128
35		Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192
34		Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671
33		Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda: Signal integrity management in an SoC physical design flow. ISPD 2003: 39-46
32		Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176
31		Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta: Static Electromigration Analysis for Signal Interconnects. ISQED 2003: 377-
30		Rajendran Panda, Savithri Sundareswaran, David Blaauw: Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Design & Test of Computers 20(3): 16-22 (2003)
29		Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003)
28		Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj: Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 337-345 (2003)
	2002
27		Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE 2002: 456-464
26		Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227
25		Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy: Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594
24		Murat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj: Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED 2002: 413-418
23		Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh: Noise Injection and Propagation in High Performance Designs. ISQED 2002: 425-430
22		Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh: False-Noise Analysis Using Resolution Method. ISQED 2002: 437-
21		Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda: Early probabilistic noise estimation for capacitively coupled interconnects. SLIP 2002: 77-83
20		Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal: Worst case clock skew under power supply variations. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 22-28
19		Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw: Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. IEEE Trans. VLSI Syst. 10(2): 79-90 (2002)
18		Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw: Hierarchical analysis of power distribution networks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 159-168 (2002)
	2001
17		Rajendran Panda, Savithri Sundareswaran, David Blaauw: On the interaction of power distribution network with substrate. ISLPED 2001: 388-393
16		David Blaauw, Rajendran Panda: On-Chip Inductance Extraction and Modelin. ISQED 2001: 14
	2000
15		David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang: On-chip inductance modeling. ACM Great Lakes Symposium on VLSI 2000: 75-80
14		Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw: Hierarchical analysis of power distribution networks. DAC 2000: 150-155
13		Rajat Chaudhry, David Blaauw, Rajendran Panda, Tim Edwards: Current signature compression for IR-drop analysis. DAC 2000: 162-167
12		David Blaauw, Rajendran Panda, Abhijit Das: Removing user specified false paths from timing graphs. DAC 2000: 270-273
11		Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw: On-chip inductance modeling and analysis. DAC 2000: 63-68
10		David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda: Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343
9		Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju: Model and analysis for combined package and on-chip power grid simulation. ISLPED 2000: 179-184
8		Rajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw: Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design 2000: 151-155
	1999
7		Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441
	1998
6		Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw: Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC 1998: 388-391
5		Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden: Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC 1998: 738-743
4		Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija: CMOS Combinational Circuit Sizing by Stage-wise Tapering. DATE 1998: 985-988
3		David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards: Emerging power management tools for processor design. ISLPED 1998: 143-148
	1997
2		Rajendran Panda, Farid N. Najm: Technology-Dependent Transformations for Low-Power Synthesis. DAC 1997: 650-655
1		Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw: Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662

Coauthor Index

1	Jacob A. Abraham	[55] [57] [58]
2	Bhuwan K. Agrawal	[20]
3	Ilan Algor	[32] [37] [39] [45]
4	Alexandre Ardelea	[36] [57]
5	David Bearden	[5]
6	Murat R. Becer	[21] [24] [25] [27] [28] [31] [32] [33] [36] [37] [38] [39] [41] [42] [45]
7	Sarvesh Bhardwaj	[50]
8	David Blaauw (David T. Blaauw)	[1] [3] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [34] [35] [36] [37] [39] [43]
9	Sri Chandrasekaran	[54]
10	Rajat Chaudhry	[8] [9] [13] [14]
11	Abhijit Das	[12]
12	Aurobindo Dasgupta	[31]
13	Abhijit Dharchoudhury	[1] [3] [4] [5] [6] [7]
14	Tim Edwards	[3] [6] [7] [8] [13] [14] [19]
15	Y. Egorov	[36]
16	Yuhong Fu	[20] [44] [48] [49] [52] [54]
17	Kaushik Gala	[11] [15] [20] [26] [29] [34]
18	Martin Gall	[40] [47]
19	Sergey Gavrilov	[1] [22] [36] [41] [42] [55]
20	Praveen Ghanta	[46] [50] [51]
21	Alexey Glebov	[1] [22] [36] [41] [42]
22	Amir Grinshpon	[25] [40] [45]
23	Ibrahim N. Hajj	[21] [24] [27] [28] [32] [37] [39]
24	Haldun Haznedar	[40] [47]
25	Haitian Hu	[26] [29] [34]
26	Jiang Hu	[53] [56]
27	Pon Sung Ku	[40] [47]
28	Rafi Levy	[25] [45]
29	Peng Li	[53] [56]
30	Trudi Mewett	[54]
31	Amit Mittal	[58]
32	S. C. Moore	[1]
33	D. Nadezhin	[36]
34	Farid N. Najm	[2]
35	Lucie Nechanicka	[55]
36	Joe Norton	[6]
37	Chanhee Oh	[3] [7] [10] [19] [22] [23] [25] [31] [32] [33] [37] [38] [39] [40] [41] [42] [45] [47]
38	Sanjay Pant	[35] [43]
39	A. Patel	[36]
40	Satyamurthy Pullela	[1] [4]
41	Ravi Ramaraju	[9]
42	R. Ramkumar	[20]
43	Ben Reschke	[52] [54]
44	Sachin S. Sapatnekar	[14] [18] [26] [29] [34]
45	Supamas Sirichotiyakul	[3] [7] [19] [25]
46	R. Soloviev	[41]
47	Roman Solovyev	[55]
48	Savithri Sundareswaran	[10] [17] [30] [35] [43] [44] [48] [49] [52] [54] [55] [57] [58]
49	Bogdan Tutuianu	[5]
50	Ravi Vaidyanathan	[5] [33] [38]
51	Gopal Vija	[4]
52	Gopalakrishnan Vijayan	[1]
53	Sarma B. K. Vrudhula	[46] [50] [51]
54	Janet Meiling Wang (Janet Meiling Wang Roveda)	[46] [51]
55	Junfeng Wang	[11] [15]
56	Shu Yan	[49] [54]
57	Xiaoji Ye	[53] [56]
58	Brian Young	[9] [11]
59	Yun Zhang	[58]
60	Min Zhao	[14] [18] [20] [26] [29] [34] [44] [48] [49] [52] [53] [54] [56]
61	Vladimir Zolotov	[9] [10] [11] [15] [20] [22] [23] [25] [26] [27] [29] [31] [32] [34] [35] [36] [37] [39] [40] [41] [42] [43] [44] [45] [47] [48]
62	Jingyan Zuo	[7]