 | 1999 |
|---|
| 6 |       | Manish Pandey,
Randal E. Bryant:
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 918-935 (1999) |
| 1997 |
|---|
| 5 | | Manish Pandey,
Randal E. Bryant:
Exploiting Symmetry When Verifying Transitor-Level Circuits by Symbolic Trajectory Evaluation.
CAV 1997: 244-255 |
| 4 | | Manish Pandey,
Richard Raimi,
Randal E. Bryant,
Magdy S. Abadir:
Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation.
DAC 1997: 167-172 |
| 1996 |
|---|
| 3 | | Manish Pandey,
Richard Raimi,
Derek L. Beatty,
Randal E. Bryant:
Formal Verification of PowerPC Arrays Using Symbolic Trajectory Evaluation.
DAC 1996: 649-654 |
| 2 |  | Neeta Ganguly,
Magdy S. Abadir,
Manish Pandey:
PowerPCTM Array Verification Methodology using Formal Techniques.
ITC 1996: 857-864 |
| 1995 |
|---|
| 1 | | Manish Pandey,
Alok Jain,
Randal E. Bryant,
Derek L. Beatty,
Gary York,
Samir Jain:
Extraction of finite state machines from transistor netlists by symbolic simulation.
ICCD 1995: 596-601 |
