Sujan Pandey

	2008
16		Sujan Pandey, Rolf Drechsler: Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. ASP-DAC 2008: 601-606
15		Sujan Pandey, Rolf Drechsler: Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. DATE 2008: 206-211
14		Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner: Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS 2008: 2989-2992
	2007
13		Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner: On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. PATMOS 2007: 242-254
12		Sujan Pandey, Christian Genz, Rolf Drechsler: Co-synthesis of custom on-chip bus and memory for MPSoC architectures. VLSI-SoC 2007: 304-307
11		Sujan Pandey, Manfred Glesner: Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. IEEE Trans. VLSI Syst. 15(10): 1111-1124 (2007)
	2006
10		Sujan Pandey, Manfred Glesner: Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. DAC 2006: 663-668
9		Sujan Pandey, Manfred Glesner: Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. FPL 2006: 1-6
8		Sujan Pandey, Manfred Glesner: Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique. ISCAS 2006
7		Sujan Pandey, Nurten Utlu, Manfred Glesner: Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. VLSI-SoC 2006: 222-227
6		Sujan Pandey, Tudor Murgan, Manfred Glesner: Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. VLSI-SoC 2006: 296-301
5		Tudor Murgan, O. Mitrea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner: Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. VLSI-SoC 2006: 302-307
	2005
4		Sujan Pandey, Manfred Glesner, Max Mühlhäuser: On-Chip Communication Topology Synthesis for a Shared Memory Architecture. FPL 2005: 374-379
3		Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser: High level hardware/software communication estimation in shared memory architecture. ISCAS (1) 2005: 37-40
2		Thomas Hollstein, Sujan Pandey, Manfred Glesner: Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. ReCoSoC 2005: 85-92
1		Sujan Pandey, Manfred Glesner, Max Mühlhäuser: Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. SBCCI 2005: 230-235

Coauthor Index

1	Petru Bogdan Bacinschi	[5] [13]
2	Rolf Drechsler	[12] [14] [15] [16]
3	Christian Genz	[12]
4	Manfred Glesner	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14]
5	Thomas Hollstein	[2]
6	O. Mitrea	[5]
7	Max Mühlhäuser	[1] [3] [4]
8	Tudor Murgan	[5] [6] [13] [14]
9	Alberto García Ortiz	[13]
10	Nurten Utlu	[7]
11	Heiko Zimmer	[3]