Marios C. Papaefthymiou

	2007
63		Zhentao Yu, Marios C. Papaefthymiou, Xun Liu: Skew spreading for peak current reduction. ACM Great Lakes Symposium on VLSI 2007: 461-464
62		Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power CoRR abs/0710.4690: (2007)
	2006
61		Jiyoun Kim, Marios C. Papaefthymiou, José Neves: Parallelizing post-placement timing optimization. IPDPS 2006
60		Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: Practical repeater insertion for low power: what repeater library do we need? IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 917-924 (2006)
	2005
59		Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou: Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers 2005: 407-413
58		Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. DATE 2005: 1330-1335
57		Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler: A GHz-class charge recovery logic. ISLPED 2005: 91-94
56		Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler: Boost Logic: A High Speed Energy Recovery Circuit Family. ISVLSI 2005: 22-27
55		Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler: Two-Phase Resonant Clock Distribution. ISVLSI 2005: 65-70
54		Jiyoun Kim, José Neves, Marios C. Papaefthymiou: Multi-Session Partitioning for Parallel Timing Optimization. PDCAT 2005: 598-602
53		Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: Charge-Recovery Computing on Silicon. IEEE Trans. Computers 54(6): 651-659 (2005)
52		Xun Liu, Marios C. Papaefthymiou: HyPE: hybrid power estimation for IP-based systems-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1089-1103 (2005)
	2004
51		Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: Practical repeater insertion for low power: what repeater library do we need? DAC 2004: 30-35
50		Jiyoun Kim, Marios C. Papaefthymiou, Athar B. Tayyab: An Algorithm for Geometric Load Balancing with Two Constraints. IPDPS 2004
49		Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou: Empirical evaluation of timing and power in resonant clock distribution. ISCAS (2) 2004: 249-252
48		Joohee Kim, Marios C. Papaefthymiou: Constant-load energy recovery memory for efficient high-speed operation. ISLPED 2004: 240-243
47		Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou: Experimental Evaluation of Resonant Clock Distribution. ISVLSI 2004: 135-140
46		Xun Liu, Marios C. Papaefthymiou: A Markov chain sequence generator for power macromodeling. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1048-1062 (2004)
	2003
45		Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman: Reduced Delay Uncertainty in High Performance Clock Distribution Networks. DATE 2003: 10068-10075
44		Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou: A 225 MHz resonant clocked ASIC chip. ISLPED 2003: 48-53
43		Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou: Energy Recovering ASIC Design. ISVLSI 2003: 133-138
42		Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: Fine-grain real-time reconfigurable pipelining. IBM Journal of Research and Development 47(5-6): 599-610 (2003)
41		Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: A true single-phase energy-recovery multiplier. IEEE Trans. VLSI Syst. 11(2): 194-207 (2003)
40		Joohee Kim, Marios C. Papaefthymiou: Block-based multiperiod dynamic memory design for low data-retention power. IEEE Trans. VLSI Syst. 11(6): 1006-1018 (2003)
39		Xun Liu, Marios C. Papaefthymiou: Design of a 20-mb/s 256-state Viterbi decoder. IEEE Trans. VLSI Syst. 11(6): 965-975 (2003)
	2002
38		Xun Liu, Marios C. Papaefthymiou: Design of a high-throughput low-power IS95 Viterbi decoder. DAC 2002: 263-268
37		Xun Liu, Marios C. Papaefthymiou: A Markov chain sequence generator for power macromodeling. ICCAD 2002: 404-411
36		Xun Liu, Marios C. Papaefthymiou: Incorporation of input glitches into power macromodeling. ISCAS (4) 2002: 846-849
35		Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: Energy recovering static memory. ISLPED 2002: 92-97
34		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Retiming and clock scheduling for digital circuit optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 184-203 (2002)
	2001
33		Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. ARVLSI 2001: 42-58
32		Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou: A True Single-Phase 8-bit Adiabatic Multiplier. DAC 2001: 758-763
31		Xun Liu, Marios C. Papaefthymiou: A static power estimation methodolodgy for IP-based design. DATE 2001: 280-289
30		Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou: A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. ISCAS (4) 2001: 422-425
29		Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou: A resonant clock generator for single-phase adiabatic systems. ISLPED 2001: 159-164
28		Suhwan Kim, Marios C. Papaefthymiou: True single-phase adiabatic circuitry. IEEE Trans. VLSI Syst. 9(1): 52-63 (2001)
27		Farinaz Koushanfar, Darko Kirovski, Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou: Symbolic debugging of embedded hardware and software. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 392-401 (2001)
	2000
26		Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou: Symbolic debugging of globally optimized behavioral specifications. ASP-DAC 2000: 397-400
25		Joohee Kim, Marios C. Papaefthymiou: Dynamic Memory Design for Low Data-Retention Power. PATMOS 2000: 207-216
24		Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak: Optimizing computations for effective block-processing. ACM Trans. Design Autom. Electr. Syst. 5(3): 604-630 (2000)
	1999
23		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Maximizing Performance by Retiming and Clock Skew Scheduling. DAC 1999: 231-236
22		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE 1999: 643-649
21		Giuseppe Bernacchia, Marios C. Papaefthymiou: Analytical macromodeling for high-level power estimation. ICCAD 1999: 280-283
20		Suhwan Kim, Marios C. Papaefthymiou: Single-phase source-coupled adiabatic logic. ISLPED 1999: 97-99
	1998
19		Marios C. Papaefthymiou: Asymptotically efficient retiming under setup and hold constraints. ICCAD 1998: 396-401
18		Suhwan Kim, Marios C. Papaefthymiou: True single-phase energy-recovering logic for low-power, high-speed VLSI. ISLPED 1998: 167-172
	1997
17		Fang Wang, Marios C. Papaefthymiou, Mark S. Squillante: Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming. JSSPP 1997: 277-298
16		Kumar N. Lalgudi, Marios C. Papaefthymiou: Retiming edge-triggered circuits under general delay models. IEEE Trans. on CAD of Integrated Circuits and Systems 16(12): 1393-1408 (1997)
15		Kumar N. Lalgudi, Marios C. Papaefthymiou: Computing Strictly-Second Shortest Paths. Inf. Process. Lett. 63(4): 177-181 (1997)
14		Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou: Optimizing two-phase, level-clocked circuitry. J. ACM 44(1): 148-199 (1997)
	1996
13		Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak: Optimizing Systems for Effective Block-Processing: The k-Delay Problem. DAC 1996: 714-719
12		Marios C. Papaefthymiou, Kumar N. Lalgudi: Fixed-phase retiming for low power design. ISLPED 1996: 259-264
11		Fang Wang, Hubertus Franke, Marios C. Papaefthymiou, Pratap Pattnaik, Larry Rudolph, Mark S. Squillante: A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. JSSPP 1996: 111-125
10		Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou: An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. SPAA 1996: 89-98
9		Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou: Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems. Perform. Eval. 27/28(4): 273-296 (1996)
	1995
8		Kumar N. Lalgudi, Marios C. Papaefthymiou: Efficient retiming under a general delay model. ARVLSI 1995: 368-382
7		Kumar N. Lalgudi, Marios C. Papaefthymiou: DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. DAC 1995: 304-309
	1994
6		Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. ICCAD 1994: 74-81
5		Anant Agarwal, John V. Guttag, Christoforos N. Hadjicostis, Marios C. Papaefthymiou: Memory Assignment for Multiprocessor Caches through Grey Coloring. PARLE 1994: 351-362
4		Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou: Precomputation-based sequential logic optimization for low power. IEEE Trans. VLSI Syst. 2(4): 426-436 (1994)
3		Marios C. Papaefthymiou: Understanding Retiming Through Maximum Avarage-Delay Cycles. Mathematical Systems Theory 27(1): 65-84 (1994)
	1993
2		Marios C. Papaefthymiou, Keith H. Randall: TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. DAC 1993: 497-502
	1991
1		Marios C. Papaefthymiou: Understanding Retiming Through Maximum Average-Weight Cycles. SPAA 1991: 338-348

Coauthor Index

1	Anant Agarwal	[5]
2	Mazhar Alidina	[4] [6]
3	Giuseppe Bernacchia	[21]
4	Juang-Ying Chueh	[47] [49] [55] [59]
5	Srinivas Devadas	[4] [6]
6	Hubertus Franke	[11]
7	Eby G. Friedman	[22] [23] [30] [34] [45]
8	Abhijit Ghosh	[4] [6]
9	John V. Guttag	[5]
10	Christoforos N. Hadjicostis	[5]
11	Inki Hong	[26] [27]
12	Alexander T. Ishii	[14]
13	Jiyoun Kim	[50] [54] [61]
14	Joohee Kim	[25] [35] [40] [43] [44] [48] [59]
15	Suhwan Kim	[18] [20] [28] [29] [32] [33] [41] [42] [53] [59]
16	Darko Kirovski	[26] [27]
17	Farinaz Koushanfar	[27]
18	Kumar N. Lalgudi	[7] [8] [12] [13] [15] [16] [24]
19	Charles E. Leiserson	[14]
20	Xun Liu	[22] [23] [31] [34] [36] [37] [38] [39] [46] [51] [52] [58] [60] [62] [63]
21	José C. Monteiro (José Monteiro)	[4] [6]
22	José Neves	[54] [61]
23	Pratap Pattnaik	[11]
24	Yuantao Peng	[51] [58] [60] [62]
25	Miodrag Potkonjak	[13] [24] [26] [27]
26	Keith H. Randall	[2]
27	Larry Rudolph	[11]
28	Visvesh S. Sathe	[44] [56] [57] [59]
29	Mark S. Squillante	[9] [10] [11] [17]
30	Athar B. Tayyab	[50]
31	Dimitrios Velenis	[30] [45]
32	Fang Wang	[9] [10] [11] [17]
33	Zhentao Yu	[63]
34	Conrad H. Ziesler	[29] [32] [33] [35] [41] [42] [43] [44] [47] [49] [53] [55] [56] [57] [59]

Colors in the list of coauthors