| 1992 |
|---|
| 8 | EE | Rajiv Jain,
Alice C. Parker,
Nohbyung Park:
Predicting system-level area and delay for pipelined and nonpipelined designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(8): 955-965 (1992) |
| 1991 |
|---|
| 7 | | James J. Kim,
Fadi J. Kurdahi,
Nohbyung Park:
Automatic Synthesis of Time-Stationary Controllers for Pipelined Data Paths.
ICCAD 1991: 30-33 |
| 1988 |
|---|
| 6 | EE | Rajiv Jain,
Alice C. Parker,
Nohbyung Park:
Module Selection for Pipelined Synthesis.
DAC 1988: 542-547 |
| 5 | | Nohbyung Park,
Alice C. Parker:
Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems.
IEEE Trans. Computers 37(6): 678-690 (1988) |
| 4 | EE | Nohbyung Park,
Alice C. Parker:
Sehwa: a software package for synthesis of pipelines from behavioral specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 356-370 (1988) |
| 1987 |
|---|
| 3 | EE | Rajiv Jain,
Alice C. Parker,
Nohbyung Park:
Predicting Area-Time Tradeoffs for Pipelined Design.
DAC 1987: 35-41 |
| 1986 |
|---|
| 2 | EE | Nohbyung Park,
Alice C. Parker:
Sehwa: a program for synthesis of pipelines.
DAC 1986: 454-460 |
| 1985 |
|---|
| 1 | EE | Nohbyung Park,
Alice C. Parker:
Synthesis of optimal clocking schemes.
DAC 1985: 489-495 |
