 | 2009 |
|---|
| 7 |       | Nishant Patil,
Albert Lin,
Jie Zhang,
H.-S. Philip Wong,
Subhasish Mitra:
Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.
DAC 2009: 304-309 |
| 6 | | Jie Zhang,
Nishant Patil,
Arash Hazeghi,
Subhasish Mitra:
Carbon nanotube circuits in the presence of carbon nanotube density variations.
DAC 2009: 71-76 |
| 5 | | Subhasish Mitra,
Jie Zhang,
Nishant Patil,
Hai Wei:
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors.
DATE 2009: 436-441 |
| 2008 |
|---|
| 4 | | Jie Zhang,
Nishant Patil,
Subhasish Mitra:
Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.
DATE 2008: 1009-1014 |
| 3 | | Nishant Patil,
Jie Deng,
Albert Lin,
H.-S. Philip Wong,
Subhasish Mitra:
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1725-1736 (2008) |
| 2007 |
|---|
| 2 | | Nishant Patil,
Jie Deng,
H.-S. Philip Wong,
Subhasish Mitra:
Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.
DAC 2007: 958-961 |
| 2005 |
|---|
| 1 | | Subhasish Mitra,
Steven S. Lumetta,
Michael Mitzenmacher,
Nishant Patil:
X-Tolerant Test Response Compaction.
IEEE Design & Test of Computers 22(6): 566-574 (2005) |
