Debjyoti Paul

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2000

2 Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan: VERILAT: verification using logic augmentation and transformations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1041-1051 (2000)

1996

1 Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee: VERILAT: verification using logic augmentation and transformations. ICCAD 1996: 88-95

	2000
2		Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan: VERILAT: verification using logic augmentation and transformations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1041-1051 (2000)
	1996
1		Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee: VERILAT: verification using logic augmentation and transformations. ICCAD 1996: 88-95

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