| 2007 |
| 22 | EE | Marco Lanuzza,
Stefania Perri,
Pasquale Corsonello,
Martin Margala:
A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications.
AHS 2007: 119-126 |
| 21 | EE | Emanuele Sciagura,
Paolo Zicari,
Stefania Perri,
Pasquale Corsonello:
An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector.
DSD 2007: 102-108 |
| 20 | EE | Pasquale Corsonello,
Stefania Perri,
G. Staino,
Marco Lanuzza,
Giuseppe Cocorullo:
Design and Implementation of a 90nm Low bit-rate Image Compression Core.
DSD 2007: 383-389 |
| 19 | EE | Marco Lanuzza,
Stefania Perri,
Pasquale Corsonello:
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing.
SAMOS 2007: 159-168 |
| 2006 |
| 18 | EE | Pasquale Corsonello,
Stefania Perri,
Martin Margala:
An integrated countermeasure against differential power analysis for secure smart-cards.
ISCAS 2006 |
| 17 | EE | Fabio Frustaci,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
Leakage energy reduction techniques in deep submicron cache memories: a comparative study.
ISCAS 2006 |
| 16 | EE | Pasquale Corsonello,
Stefania Perri,
G. Staino,
Marco Lanuzza,
Giuseppe Cocorullo:
Low bit rate image compression core for onboard space applications.
IEEE Trans. Circuits Syst. Video Techn. 16(1): 114-128 (2006) |
| 15 | EE | Fabio Frustaci,
Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories.
IEEE Trans. VLSI Syst. 14(11): 1238-1249 (2006) |
| 14 | EE | Stefania Perri,
Maria Antonia Iachino,
Pasquale Corsonello:
Simd Multipliers for Accelerating Embedded Processors in FPGAS.
Journal of Circuits, Systems, and Computers 15(4): 537-550 (2006) |
| 2005 |
| 13 | | Marco Lanuzza,
Stefania Perri,
Martin Margala,
Pasquale Corsonello:
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor.
FPL 2005: 13-18 |
| 12 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
Fast Low-Power 64-Bit Modular Hybrid Adder.
PATMOS 2005: 609-617 |
| 11 | EE | Pasquale Corsonello,
Stefania Perri:
Efficient Reconfigurable Manchester Adders for Low-power Media Processing.
Journal of Circuits, Systems, and Computers 14(1): 57-64 (2005) |
| 10 | EE | Pasquale Corsonello,
Stefania Perri,
Paolo Zicari,
Giuseppe Cocorullo:
Microprocessor-based FPGA implementation of SPIHT image compression subsystems.
Microprocessors and Microsystems 29(6): 299-305 (2005) |
| 9 | EE | Stefania Perri,
Marco Lanuzza,
Pasquale Corsonello,
Giuseppe Cocorullo:
A high-performance fully reconfigurable FPGA-based 2D convolution processor.
Microprocessors and Microsystems 29(8-9): 381-391 (2005) |
| 2004 |
| 8 | | Pasquale Corsonello,
Stefania Perri,
Vitit Kantabutra:
Area- and Power-Reduced Standard-Cell Spanning Tree Adders.
ESA/VLSI 2004: 343-352 |
| 7 | EE | Stefania Perri,
Pasquale Corsonello,
Maria Antonia Iachino,
Marco Lanuzza,
Giuseppe Cocorullo:
Variable precision arithmetic circuits for FPGA-based multimedia processors.
IEEE Trans. VLSI Syst. 12(9): 995-999 (2004) |
| 2003 |
| 6 | EE | Pasquale Corsonello,
Stefania Perri,
Maria Antonia Iachino,
Giuseppe Cocorullo:
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems.
FPL 2003: 661-669 |
| 5 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
A high-speed energy-efficient 64-bit reconfigurable binary adder.
IEEE Trans. VLSI Syst. 11(5): 939-943 (2003) |
| 2002 |
| 4 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
VLSI circuits for low-power high-speed asynchronous addition.
IEEE Trans. VLSI Syst. 10(5): 608-613 (2002) |
| 2000 |
| 3 | EE | Stefania Perri,
Pasquale Corsonello,
Giuseppe Cocorullo:
Designing High-Speed Asynchronous Pipelines.
EUROMICRO 2000: 1394-1399 |
| 2 | EE | Pasquale Corsonello,
Stefania Perri,
Giuseppe Cocorullo:
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder.
PATMOS 2000: 195-204 |
| 1 | EE | Pasquale Corsonello,
Stefania Perri,
G. Cororullo:
Area-time-power tradeoff in cellular arrays VLSI implementations.
IEEE Trans. VLSI Syst. 8(5): 614-624 (2000) |