 | 2012 |
| 39 |  | Robin Bonamy,
Hung-Manh Pham,
Sébastien Pillement,
Daniel Chillet:
UPaRC - Ultra-fast power-aware reconfiguration controller.
DATE 2012: 1373-1378 |
| 2011 |
| 38 |  | Hung-Manh Pham,
Sébastien Pillement,
Olivier Pasquier,
Sébastien LeNours:
A framework for the design of reconfigurable fault tolerant architectures.
DASIP 2011: 324-331 |
| 37 |  | Muhammad Moazam Azeem,
Stanislaw J. Piestrak,
Olivier Sentieys,
Sébastien Pillement:
Error recovery technique for coarse-grained reconfigurable architectures.
DDECS 2011: 441-446 |
| 36 |  | Antoine Eiche,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
Parallel Evaluation of Hopfield Neural Networks.
IJCCI (NCTA) 2011: 248-253 |
| 35 |  | Hung-Manh Pham,
Ludovic Devaux,
Sébastien Pillement:
Re2DA: Reliable and reconfigurable dynamic architecture.
ReCoSoC 2011: 1-6 |
| 34 |  | Surya Narayanan,
Daniel Chillet,
Sébastien Pillement,
Ioannis Sourdis:
Hardware OS Communication Service and Dynamic Memory Management for RSoCs.
ReConFig 2011: 117-122 |
| 33 |  | Surya Narayanan,
Ludovic Devaux,
Daniel Chillet,
Sébastien Pillement,
Ioannis Sourdis:
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources.
VLSI-SoC 2011: 196-199 |
| 32 |  | Daniel Chillet,
Antoine Eiche,
Sébastien Pillement,
Olivier Sentieys:
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network.
Journal of Systems Architecture - Embedded Systems Design 57(4): 340-353 (2011) |
| 2010 |
| 31 |  | Antoine Eiche,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
Task placement for dynamic and partial reconfigurable architecture.
DASIP 2010: 228-234 |
| 30 |  | Hung-Manh Pham,
Sébastien Pillement,
Didier Demigny:
Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC.
FPL 2010: 159-162 |
| 29 |  | Syed M. A. H. Jafri,
Stanislaw J. Piestrak,
Olivier Sentieys,
Sébastien Pillement:
Design of a fault-tolerant coarse-grained.
ISQED 2010: 845-852 |
| 28 |  | Ludovic Devaux,
Sébastien Pillement,
Daniel Chillet,
Didier Demigny:
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip.
ReConFig 2010: 376-381 |
| 27 |  | Stanislaw J. Piestrak,
Sébastien Pillement,
Olivier Sentieys:
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication".
IEEE Communications Letters 14(8): 761-763 (2010) |
| 26 |  | Stanislaw J. Piestrak,
Sébastien Pillement,
Olivier Sentieys:
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication.
IEEE Trans. on Circuits and Systems 57-II(10): 777-781 (2010) |
| 25 |  | Ludovic Devaux,
Sana Ben Sassi,
Sébastien Pillement,
Daniel Chillet,
Didier Demigny:
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures.
Int. J. Reconfig. Comp. 2010: (2010) |
| 24 |  | Sébastien Pillement,
Olivier Sentieys,
Jean-Marc Philippe:
Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect.
Microelectronics Journal 41(8): 480-486 (2010) |
| 2009 |
| 23 |  | Julien Lallet,
Sébastien Pillement,
Olivier Sentieys:
xMAML: A Modeling Language for Dynamically Reconfigurable Architectures.
DSD 2009: 680-687 |
| 22 |  | Sébastien Pillement,
Daniel Chillet,
Yaset Oliva,
Jean-Christophe Prévotet:
High-Level Exploration for Dynamic Reconfiguration Management.
ERSA 2009: 301-302 |
| 21 |  | Hung-Manh Pham,
Sébastien Pillement,
Didier Demigny:
A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip.
ReConFig 2009: 284-289 |
| 20 |  | Benoit Miramond,
Emmanuel Huck,
François Verdier,
Mohamed El Amine Benkhelifa,
Bertrand Granado,
Thomas LeFebvre,
Mehdi Aïchouch,
Jean-Christophe Prévotet,
Yaset Oliva,
Daniel Chillet,
Sébastien Pillement:
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms.
Int. J. Reconfig. Comp. 2009: (2009) |
| 2008 |
| 19 |  | Jean-Christophe Prévotet,
Mohamed El Amine Benkhelifa,
Bertrand Granado,
Emmanuel Huck,
Benoit Miramond,
François Verdier,
Daniel Chillet,
Sébastien Pillement:
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources.
ReConFig 2008: 61-66 |
| 18 |  | Julien Lallet,
Sébastien Pillement,
Olivier Sentieys:
Efficient dynamic reconfiguration for multi-context embedded FPGA.
SBCCI 2008: 210-215 |
| 17 |  | Sébastien Pillement,
Olivier Sentieys,
Raphaël David:
DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency.
EURASIP J. Emb. Sys. 2008: (2008) |
| 2007 |
| 16 |  | Alexey Kupriyanov,
Frank Hannig,
Dmitrij Kissler,
Jürgen Teich,
Julien Lallet,
Olivier Sentieys,
Sébastien Pillement:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures.
ARCS 2007: 268-282 |
| 15 |  | Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures.
IJCNN 2007: 102-107 |
| 14 |  | Sébastien Pillement,
Raphaël David:
Architectures reconfigurable et faible consommation. Réalité ou prospective ?
Technique et Science Informatiques 26(5): 595-621 (2007) |
| 2006 |
| 13 |  | Jean-Marc Philippe,
E. Kinvi-Boh,
Sébastien Pillement,
Olivier Sentieys:
An energy-efficient ternary interconnection link for asynchronous systems.
ISCAS 2006 |
| 12 |  | Jean-Marc Philippe,
Sébastien Pillement,
Olivier Sentieys:
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects.
ISQED 2006: 334-339 |
| 11 |  | Nicolas Abel,
Lounis Kessal,
Sébastien Pillement,
Didier Demigny:
Clear Stream towards Dynamically Reconfigurable Systems on Chip.
ReCoSoC 2006: 98-104 |
| 2005 |
| 10 |  | Jean-Marc Philippe,
Sébastien Pillement,
Olivier Sentieys:
A low-power and high-speed quaternary interconnection link using efficient converters.
ISCAS (5) 2005: 4689-4692 |
| 9 |  | François Verdier,
Jean-Christophe Prévotet,
Mohamed El Amine Benkhelifa,
Daniel Chillet,
Sébastien Pillement:
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform.
ReCoSoC 2005: 71-78 |
| 8 |  | Raphaël David,
Dominique Lavenier,
Sébastien Pillement:
Du microprocesseur au circuit FPGA. Une analyse sous l'angle de la reconfiguration.
Technique et Science Informatiques 24(4): 395-422 (2005) |
| 2002 |
| 7 |  | Raphaël David,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
A Compilation Framework for a Dynamically Reconfigurable Architecture.
FPL 2002: 1058-1067 |
| 6 |  | Raphaël David,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints.
IPDPS 2002 |
| 5 |  | Sébastien Pillement,
Daniel Chillet,
Olivier Sentieys:
Behavioral IP Specification and Integration Framework for High-Level Design Reuse.
ISQED 2002: 388-393 |
| 2001 |
| 4 |  | Raphaël David,
Daniel Chillet,
Sébastien Pillement,
Olivier Sentieys:
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals.
VLSI-SOC 2001: 51-62 |
| 1999 |
| 3 |  | Sébastien Pillement,
Lionel Torres,
Michel Robert,
Gaston Cambon:
Fast Prototyping: A Case Study - The JPEG Compression Algorithm.
IEEE International Workshop on Rapid System Prototyping 1999: 87- |
| 2 |  | S. Raimbault,
Gilles Sassatelli,
Gamille Cambon,
Michel Robert,
Sébastien Pillement,
Lionel Torres:
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.
VLSI 1999: 407-414 |
| 1996 |
| 1 |  | Sébastien Pillement,
Lionel Torres,
Michel Robert,
Gaston Cambon:
Concurrent Design of Hardware/Software Dedicated Systems.
FPL 1996: 410-414 |