Luis A. Plana

	2009
14		Javier Navaridas, Mikel Luján, José Miguel-Alonso, Luis A. Plana, Steve Furber: Understanding the interconnection network of SpiNNaker. ICS 2009: 286-295
	2008
13		Shufan Yang, Steve Furber, Yebin Shi, Luis A. Plana: An admission control system for QoS provision on a best-effort GALS interconnect. ACSD 2008: 200-207
12		Andrew D. Brown, David R. Lester, Luis A. Plana, Steve Furber, Peter R. Wilson: SpiNNaker: The Design Automation Problem. ICONIP (2) 2008: 1049-1056
11		M. M. Khan, David R. Lester, Luis A. Plana, Alexander D. Rast, X. Jin, E. Painkras, Stephen B. Furber: SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. IJCNN 2008: 2849-2856
10		Luis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu: An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. NOCS 2008: 215-216
	2007
9		Luis A. Plana, Doug Edwards, Sam Taylor, Luis A. Tarazona, Andrew Bardsley: Performance-driven syntax-directed synthesis of asynchronous processors. CASES 2007: 43-47
8		Luis A. Plana, Stephen B. Furber, Steve Temple, Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang: A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Design & Test of Computers 24(5): 454-463 (2007)
	2005
7		Luis A. Plana, Sam Taylor, Doug Edwards: Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance. ICCD 2005: 703-710
	2004
6		W. J. Bainbridge, Luis A. Plana, Stephen B. Furber: The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip. DATE 2004: 274-279
	2003
5		Z. C. Yu, Stephen B. Furber, Luis A. Plana: An Investigation into the Security of Self-Timed Circuits. ASYNC 2003: 206-215
4		Luis A. Plana, P. A. Riocreux, W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, Z. C. Yu: SPA - a secure Amulet core for smartcard applications. Microprocessors and Microsystems 27(9): 431-446 (2003)
	2002
3		W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, P. A. Riocreux, Luis A. Plana: SPA - A Synthesisable Amulet Core for Smartcard pplications. ASYNC 2002: 201-210
	1998
2		Luis A. Plana, Steven M. Nowick: Architectural optimization for low-power nonpipelined asynchronous systems. IEEE Trans. VLSI Syst. 6(1): 56-65 (1998)
	1996
1		Luis A. Plana, Steven M. Nowick: Concurrency-oriented optimization for low-power asynchronous systems. ISLPED 1996: 151-156

Coauthor Index

1	John Bainbridge	[10]
2	W. J. Bainbridge	[3] [4] [6]
3	Andrew Bardsley	[3] [4] [9]
4	Andrew D. Brown	[12]
5	Doug Edwards	[7] [9]
6	Stephen B. Furber (Steve Furber)	[5] [6] [8] [10] [11] [12] [13] [14]
7	Jim D. Garside	[3] [4]
8	X. Jin	[11]
9	M. M. Khan	[11]
10	Mukaram Khan	[8]
11	David R. Lester	[11] [12]
12	Mikel Luján	[14]
13	José Miguel-Alonso	[14]
14	Javier Navaridas	[14]
15	Steven M. Nowick	[1] [2]
16	E. Painkras	[11]
17	Alexander D. Rast	[11]
18	P. A. Riocreux	[3] [4]
19	Sean Salisbury	[10]
20	Yebin Shi	[8] [10] [13]
21	Luis A. Tarazona	[9]
22	Sam Taylor	[7] [9]
23	Steve Temple	[3] [4] [8]
24	Peter R. Wilson	[12]
25	Jian Wu	[8] [10]
26	Shufan Yang	[8] [13]
27	Z. C. Yu	[4] [5]