 | 2009 |
| 23 |  | Peter Malík,
Michal Ufnal,
Arkadiusz W. Luczyk,
Marcel Baláz,
Witold A. Pleskacz:
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio.
DDECS 2009: 144-147 |
| 22 |  | Krzysztof Marcinek,
Arkadiusz W. Luczyk,
Witold A. Pleskacz:
Enhanced LEON3 core for superscalar processing.
DDECS 2009: 238-241 |
| 21 |  | Jacek Gradzki,
Tomasz Borejko,
Witold A. Pleskacz:
Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS.
DDECS 2009: 78-83 |
| 2008 |
| 20 |  | Artur L. Sobczyk,
Arkadiusz W. Luczyk,
Witold A. Pleskacz:
Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures.
DDECS 2008: 14-17 |
| 19 |  | Peter Malík,
Marcel Baláz,
Martin Simlastík,
Arkadiusz W. Luczyk,
Witold A. Pleskacz:
Various MDCT implementations in 0.35µm CMOS.
DDECS 2008: 170-173 |
| 18 |  | Marcin J. Beresinski,
Tomasz Borejko,
Witold A. Pleskacz,
Viera Stopjaková:
Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology.
DDECS 2008: 259-262 |
| 17 |  | Tomasz Borejko,
Witold A. Pleskacz:
A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations.
DDECS 2008: 38-43 |
| 16 |  | Witold A. Pleskacz,
Maksim Jenihhin,
Jaan Raik,
Michal Rakowski,
Raimund Ubar,
Wieslaw Kuzmicz:
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC.
DSD 2008: 729-734 |
| 2007 |
| 15 |  | Artur L. Sobczyk,
Arkadiusz W. Luczyk,
Witold A. Pleskacz:
Power Dissipation in Basic Global Clock Distribution Networks.
DDECS 2007: 231-234 |
| 14 |  | Maksim Jenihhin,
Jaan Raik,
Raimund Ubar,
Witold A. Pleskacz,
Michal Rakowski:
Layout to Logic Defect Analysis for Hierarchical Test Generation.
DDECS 2007: 35-40 |
| 13 |  | Zbigniew Piatek,
Jerzy F. Kolodziejski,
Witold A. Pleskacz:
ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing.
DDECS 2007: 423-428 |
| 2005 |
| 12 |  | Joachim Sudbrock,
Jaan Raik,
Raimund Ubar,
Wieslaw Kuzmicz,
Witold A. Pleskacz:
Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs.
DSD 2005: 79-82 |
| 2003 |
| 11 |  | Dominik Kasprowicz,
Witold A. Pleskacz:
Improvement of integrated circuit testing reliability by using the defect based approach.
Microelectronics Reliability 43(6): 945-953 (2003) |
| 2002 |
| 10 |  | Witold A. Pleskacz,
Tomasz Borejko,
Wieslaw Kuzmicz:
CMOS Standard Cells Characterization for IDDQ Testing.
DFT 2002: 390-398 |
| 9 |  | T. Cibáková,
María Fischerová,
Elena Gramatová,
Wieslaw Kuzmicz,
Witold A. Pleskacz,
Jaan Raik,
Raimund Ubar:
Hierarchical test generation for combinational circuits with real defects coverage.
Microelectronics Reliability 42(7): 1141-1149 (2002) |
| 2001 |
| 8 |  | Witold A. Pleskacz,
Dominik Kasprowicz,
Tomasz Oleszczak,
Wieslaw Kuzmicz:
CMOS Standard Cells Characterization for Defect Based Testing.
DFT 2001: 384- |
| 7 |  | Wieslaw Kuzmicz,
Witold A. Pleskacz,
Jaan Raik,
Raimund Ubar:
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits.
ISQED 2001: 365-371 |
| 6 |  | Mykola Blyzniuk,
Irena Kazymyra,
Wieslaw Kuzmicz,
Witold A. Pleskacz,
Jaan Raik,
Raimund Ubar:
Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement.
Microelectronics Reliability 41(12): 2023-2040 (2001) |
| 1999 |
| 5 |  | Witold A. Pleskacz:
Yield Estimation of VLSI Circuits with Downscaled Layouts.
DFT 1999: 55-60 |
| 4 |  | Witold A. Pleskacz,
Charles H. Ouyang,
Wojciech Maly:
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 151-162 (1999) |
| 1997 |
| 3 |  | Hans T. Heineken,
Jitendra Khare,
Wojciech Maly,
Pranab K. Nag,
Charles H. Ouyang,
Witold A. Pleskacz:
CAD at the Design-Manufacturing Interface.
DAC 1997: 321-326 |
| 2 |  | Witold A. Pleskacz,
Wojciech Maly:
Improved Yield Model for Submicron Domain.
DFT 1997: 2-10 |
| 1 |  | Witold A. Pleskacz,
Wojciech Maly,
Hans T. Heineken:
Detection of Yield Trends.
DFT 1997: 62-68 |