 | 2009 |
|---|
| 140 |       | Cesare Ferri,
R. Iris Bahar,
Mirko Loghi,
Massimo Poncino:
Energy-optimal synchronization primitives for single-chip multi-processors.
ACM Great Lakes Symposium on VLSI 2009: 141-144 |
| 139 | | Karthik Duraisami,
Enrico Macii,
Massimo Poncino:
Using soft-edge flip-flops to compensate NBTI-induced delay degradation.
ACM Great Lakes Symposium on VLSI 2009: 169-172 |
| 138 | | Andrea Calimera,
Enrico Macii,
Massimo Poncino:
NBTI-aware sleep transistor design for reliable power-gating.
ACM Great Lakes Symposium on VLSI 2009: 333-338 |
| 137 | | Leticia Maria Veiras Bolzani,
Andrea Calimera,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Enabling concurrent clock and power gating in an industrial design flow.
DATE 2009: 334-339 |
| 136 | | Andrea Calimera,
Enrico Macii,
Massimo Poncino:
NBTI-aware power gating for concurrent leakage and aging optimization.
ISLPED 2009: 127-132 |
| 135 | | Franco Fummi,
Mirko Loghi,
Massimo Poncino,
Graziano Pravadelli:
A cosimulation methodology for HW/SW validation and performance estimation.
ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
| 2008 |
|---|
| 134 | | Ashoka Visweswara Sathanur,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Optimal sleep transistor synthesis under timing and area constraints.
ACM Great Lakes Symposium on VLSI 2008: 177-182 |
| 133 | | Karthik Duraisami,
Enrico Macii,
Massimo Poncino:
Energy efficiency bounds of pulse-encoded buses.
ACM Great Lakes Symposium on VLSI 2008: 183-188 |
| 132 | | Andrea Calimera,
Enrico Macii,
Massimo Poncino,
R. Iris Bahar:
Temperature-insensitive synthesis using multi-vt libraries.
ACM Great Lakes Symposium on VLSI 2008: 5-10 |
| 131 | | Ashoka Visweswara Sathanur,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
A Scalable Algorithmic Framework for Row-Based Power-Gating.
DATE 2008: 379-384 |
| 130 | | Enrico Macii,
Leticia Maria Veiras Bolzani,
Andrea Calimera,
Alberto Macii,
Massimo Poncino:
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.
DSD 2008: 298-303 |
| 129 | | Ashoka Visweswara Sathanur,
Andrea Calimera,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.
ISCAS 2008: 2761-2764 |
| 128 | | Andrea Calimera,
R. Iris Bahar,
Enrico Macii,
Massimo Poncino:
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.
ISLPED 2008: 217-220 |
| 127 | | Ashoka Visweswara Sathanur,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.
ISLPED 2008: 51-56 |
| 126 | | Ashoka Visweswara Sathanur,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.
PATMOS 2008: 42-51 |
| 125 | | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.
IEEE Trans. VLSI Syst. 16(6): 639-649 (2008) |
| 124 | | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.
Integration 41(1): 2-8 (2008) |
| 2007 |
|---|
| 123 | | Olga Golubeva,
Mirko Loghi,
Massimo Poncino:
On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors.
ACM Great Lakes Symposium on VLSI 2007: 489-492 |
| 122 | | Andrea Calimera,
Antonio Pullini,
Ashoka Visweswara Sathanur,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.
ACM Great Lakes Symposium on VLSI 2007: 501-504 |
| 121 | | Ashoka Visweswara Sathanur,
Andrea Calimera,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
DATE 2007: 1544-1549 |
| 120 | | Olga Golubeva,
Mirko Loghi,
Massimo Poncino,
Enrico Macii:
Architectural leakage-aware management of partitioned scratchpad memories.
DATE 2007: 1665-1670 |
| 119 | | Karthik Duraisami,
Prassanna Sithambaram,
Ashoka Visweswara Sathanur,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.
ISCAS 2007: 1061-1064 |
| 118 | | Ashoka Visweswara Sathanur,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Timing-driven row-based power gating.
ISLPED 2007: 104-109 |
| 117 | | Olga Golubeva,
Mirko Loghi,
Enrico Macii,
Massimo Poncino:
Locality-driven architectural cache sub-banking for leakage energy reduction.
ISLPED 2007: 274-279 |
| 116 | | Mirko Loghi,
Luca Benini,
Massimo Poncino:
Power macromodeling of MPSoC message passing primitives.
ACM Trans. Embedded Comput. Syst. 6(4): (2007) |
| 115 | | Francesco Poletti,
Antonio Poggiali,
Davide Bertozzi,
Luca Benini,
Pol Marchal,
Mirko Loghi,
Massimo Poncino:
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.
IEEE Trans. Computers 56(5): 606-621 (2007) |
| 2006 |
|---|
| 114 | | Franco Fummi,
Giovanni Perbellini,
Mirko Loghi,
Massimo Poncino:
ISS-centric modular HW/SW co-simulation.
ACM Great Lakes Symposium on VLSI 2006: 31-36 |
| 113 | | Kimish Patel,
Luca Benini,
Enrico Macii,
Massimo Poncino:
STV-Cache: a leakage energy-efficient architecture for data caches.
ACM Great Lakes Symposium on VLSI 2006: 404-409 |
| 112 | | Ashutosh Chakraborty,
Prassanna Sithambaram,
Karthik Duraisami,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Thermal resilient bounded-skew clock tree optimization methodology.
DATE 2006: 832-837 |
| 111 | | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.
ISCAS 2006 |
| 110 | | A. Nurrachmat,
Enrico Macii,
Massimo Poncino:
Low-energy pixel approximation for DVI-based LCD interfaces.
ISCAS 2006 |
| 109 | | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic thermal clock skew compensation using tunable delay buffers.
ISLPED 2006: 162-167 |
| 108 | | Mirko Loghi,
Massimo Poncino,
Luca Benini:
Synchronization-driven dynamic speed scaling for MPSoCs.
ISLPED 2006: 346-349 |
| 107 | | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.
PATMOS 2006: 214-224 |
| 106 | | Mirko Loghi,
Massimo Poncino,
Luca Benini:
Cache coherence tradeoffs in shared-memory MPSoCs.
ACM Trans. Embedded Comput. Syst. 5(2): 383-407 (2006) |
| 105 | | Kimish Patel,
Luca Benini,
Enrico Macii,
Massimo Poncino:
Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2626-2637 (2006) |
| 104 | | Kimish Patel,
Enrico Macii,
Massimo Poncino,
Luca Benini:
Energy-Efficient Value Based Selective Refresh for Embedded DRAMS.
J. Low Power Electronics 2(1): 70-79 (2006) |
| 2005 |
|---|
| 103 | | Mirko Loghi,
Martin Letis,
Luca Benini,
Massimo Poncino:
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors.
ACM Great Lakes Symposium on VLSI 2005: 276-281 |
| 102 | | Kimish Patel,
Enrico Macii,
Massimo Poncino:
Zero clustering: an approach to extend zero compression to instruction caches.
ACM Great Lakes Symposium on VLSI 2005: 56-59 |
| 101 | | Mirko Loghi,
Massimo Poncino:
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions.
DATE 2005: 508-513 |
| 100 | | Mirko Loghi,
Paolo Azzoni,
Massimo Poncino:
Tag Overflow Buffering: An Energy-Efficient Cache Architecture.
DATE 2005: 520-525 |
| 99 | | Franco Fummi,
Mirko Loghi,
Stefano Martini,
Marco Monguzzi,
Giovanni Perbellini,
Massimo Poncino:
Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation.
DATE 2005: 798-803 |
| 98 | | Andi Nourrachmat,
Sabino Salerno,
Enrico Macii,
Massimo Poncino:
Energy-Efficient Color Approximation for Digital LCD Interfaces.
ICCD 2005: 81-86 |
| 97 | | Kimish Patel,
Enrico Macii,
Massimo Poncino:
Frame Buffer Energy Optimization by Pixel Prediction.
ICCD 2005: 98-101 |
| 96 | | Ashutosh Chakraborty,
Enrico Macii,
Massimo Poncino:
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.
PATMOS 2005: 297-307 |
| 95 | | Kimish Patel,
Luca Benini,
Enrico Macii,
Massimo Poncino:
Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs.
PATMOS 2005: 466-476 |
| 2004 |
|---|
| 94 | | Alberto Bocca,
Sabino Salerno,
Enrico Macii,
Massimo Poncino:
Energy-efficient bus encoding for LCD displays.
ACM Great Lakes Symposium on VLSI 2004: 240-243 |
| 93 | | Mirko Loghi,
Massimo Poncino,
Luca Benini:
Cycle-accurate power analysis for multiprocessor systems-on-a-chip.
ACM Great Lakes Symposium on VLSI 2004: 410-406 |
| 92 | | Franco Fummi,
Stefano Martini,
Giovanni Perbellini,
Massimo Poncino,
Fabio Ricciato,
Maura Turolla:
Heterogeneous Co-Simulation of Networked Embedded Systems.
DATE 2004: 168-173 |
| 91 |  | Franco Fummi,
Stefano Martini,
Marco Monguzzi,
Giovanni Perbellini,
Massimo Poncino:
Modeling and Analysis of Heterogeneous Industrial Networks Architectures.
DATE 2004: 342-344 |
| 90 | | Franco Fummi,
Stefano Martini,
Giovanni Perbellini,
Massimo Poncino:
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC.
DATE 2004: 564-569 |
| 89 | | Kimish Patel,
Enrico Macii,
Massimo Poncino:
Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC.
DATE 2004: 700-701 |
| 88 | | Kimish Patel,
Enrico Macii,
Luca Benini,
Massimo Poncino:
Reducing cache misses by application-specific re-configurable indexing.
ICCAD 2004: 125-130 |
| 87 | | Massimo Poncino,
Jianwen Zhu:
DynamoSim: a trace-based dynamically compiled instruction set simulator.
ICCAD 2004: 131-136 |
| 86 | | Mirko Loghi,
Luca Benini,
Massimo Poncino:
Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor.
ICCD 2004: 393-396 |
| 85 | | Franco Fummi,
Stefano Martini,
Marco Monguzzi,
Giovanni Perbellini,
Massimo Poncino:
Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures.
ICCD 2004: 496-501 |
| 84 | | Kimish Patel,
Enrico Macii,
Massimo Poncino:
Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip.
ISCAS (2) 2004: 361-364 |
| 83 | | Sabino Salerno,
Enrico Macii,
Massimo Poncino:
Crosstalk energy reduction by temporal shielding.
ISCAS (2) 2004: 749-752 |
| 82 | | Sabino Salerno,
Alberto Bocca,
Enrico Macii,
Massimo Poncino:
Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces.
ISLPED 2004: 206-211 |
| 81 | | Sabino Salerno,
Enrico Macii,
Massimo Poncino:
A Low-Power Encoding Scheme for GigaByte Video Interfaces.
PATMOS 2004: 58-68 |
| 2003 |
|---|
| 80 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Elvira Omerbegovic,
Massimo Poncino,
Fabrizio Pro:
A novel architecture for power maskable arithmetic units.
ACM Great Lakes Symposium on VLSI 2003: 136-140 |
| 79 | | Enrico Macii,
Massimo Poncino,
Sabino Salerno:
Combining wire swapping and spacing for low-power deep-submicron buses.
ACM Great Lakes Symposium on VLSI 2003: 198-202 |
| 78 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Elvira Omerbegovic,
Fabrizio Pro,
Massimo Poncino:
Energy-aware design techniques for differential power analysis protection.
DAC 2003: 36-41 |
| 77 | | Franco Fummi,
Giovanni Perbellini,
Paolo Gallo,
Massimo Poncino,
Stefano Martini,
Fabio Ricciato:
A timing-accurate modeling and simulation environment for networked embedded systems.
DAC 2003: 42-47 |
| 76 | | Alberto Macii,
Enrico Macii,
Massimo Poncino:
Improving the Efficiency of Memory Partitioning by Address Clustering.
DATE 2003: 10018-10023 |
| 75 | | Nicola Drago,
Franco Fummi,
Marco Monguzzi,
Giovanni Perbellini,
Massimo Poncino:
Estimation of Bus Performance for a Tuplespace in an Embedded Architecture.
DATE 2003: 20188-20195 |
| 74 | | Alberto Macii,
Enrico Macii,
Massimo Poncino:
Increasing the locality of memory access patterns by low-overhead hardware address relocation.
ISCAS (5) 2003: 385-388 |
| 73 | | Luca Benini,
Angelo Galati,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Energy-efficient data scrambling on memory-processor interfaces.
ISLPED 2003: 26-29 |
| 72 | | Alessandro Fin,
Franco Fummi,
Massimo Poncino,
Graziano Pravadelli:
A SystemC-based Framework for Properties Incompleteness Evaluation.
MTV 2003: 89-94 |
| 71 | | Maurizio Bruno,
Alberto Macii,
Massimo Poncino:
A Statistic Power Model for Non-synthetic RTL Operators.
PATMOS 2003: 208-218 |
| 70 | | Luca Benini,
Alberto Macii,
Massimo Poncino:
Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques.
ACM Trans. Embedded Comput. Syst. 2(1): 5-32 (2003) |
| 69 | | Luca Benini,
Davide Bertozzi,
Davide Bruni,
Nicola Drago,
Franco Fummi,
Massimo Poncino:
SystemC Cosimulation and Emulation of Multiprocessor SoC Designs.
IEEE Computer 36(4): 53-59 (2003) |
| 68 | | Luca Benini,
Davide Bruni,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Discharge Current Steering for Battery Lifetime Optimization.
IEEE Trans. Computers 52(8): 985-995 (2003) |
| 67 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Scheduling battery usage in mobile systems.
IEEE Trans. VLSI Syst. 11(6): 1136-1143 (2003) |
| 2002 |
|---|
| 66 | | Monica Donno,
Luca Macchiarulo,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Enhanced clustered voltage scaling for low power.
ACM Great Lakes Symposium on VLSI 2002: 18-23 |
| 65 | | Luca Macchiarulo,
Enrico Macii,
Massimo Poncino:
Wire Placement for Crosstalk Energy Minimization in Address Buses.
DATE 2002: 158-162 |
| 64 | | Luca Benini,
Davide Bertozzi,
Davide Bruni,
Nicola Drago,
Franco Fummi,
Massimo Poncino:
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip.
ICCD 2002: 494-499 |
| 63 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Discharge current steering for battery lifetime optimization.
ISLPED 2002: 118-123 |
| 62 | | Luca Benini,
Luca Macchiarulo,
Alberto Macii,
Massimo Poncino:
Layout-driven memory synthesis for embedded systems-on-chip.
IEEE Trans. VLSI Syst. 10(2): 96-105 (2002) |
| 61 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Minimizing memory access energy in embedded systems by selective instruction compression.
IEEE Trans. VLSI Syst. 10(5): 521-531 (2002) |
| 2001 |
|---|
| 60 | | Luca Benini,
Luca Macchiarulo,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.
DAC 2001: 784-789 |
| 59 | | Luca Benini,
Giuliano Castelli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Extending lifetime of portable systems by battery scheduling.
DATE 2001: 197-203 |
| 58 | | Luca Macchiarulo,
Enrico Macii,
Massimo Poncino:
Low-energy for deep-submicron address buses.
ISLPED 2001: 176-181 |
| 57 | | Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Stream synthesis for efficient power simulation based on spectral transforms.
IEEE Trans. VLSI Syst. 9(3): 417-426 (2001) |
| 56 | | Luca Benini,
Giuliano Castelli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Discrete-time battery models for system-level low-power design.
IEEE Trans. VLSI Syst. 9(5): 630-640 (2001) |
| 55 | | Alessandro Bogliolo,
Roberto Corgnati,
Enrico Macii,
Massimo Poncino:
Parameterized RTL power models for soft macros.
IEEE Trans. VLSI Syst. 9(6): 880-887 (2001) |
| 54 | | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Synthesis of power-managed sequential components based oncomputational kernel extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1118-1131 (2001) |
| 2000 |
|---|
| 53 | | Luca Benini,
Alessandro Bogliolo,
Enrico Macii,
Massimo Poncino,
Mihai Surmei:
Regression-based RTL power models for controllers.
ACM Great Lakes Symposium on VLSI 2000: 147-152 |
| 52 | | Luca Benini,
Marco Ferrero,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Supporting system-level power exploration for DSP applications.
ACM Great Lakes Symposium on VLSI 2000: 17-22 |
| 51 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Synthesis of application-specific memories for power optimization in embedded systems.
DAC 2000: 300-303 |
| 50 | | Luca Benini,
Giuliano Castelli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
A Discrete-Time Battery Model for High-Level Power Estimation.
DATE 2000: 35- |
| 49 | | Luca Benini,
Alberto Macii,
Massimo Poncino:
A recursive algorithm for low-power memory partitioning.
ISLPED 2000: 78-83 |
| 48 | | Roberto Zafalon,
Massimo Rossello,
Enrico Macii,
Massimo Poncino:
Power Macromodeling for a High Quality RT-Level Power Estimation.
ISQED 2000: 59- |
| 47 | | Alessandro Bogliolo,
Enrico Macii,
Virgil Mihailovici,
Massimo Poncino:
Power Models for Semi-autonomous RTL Macros.
PATMOS 2000: 14-23 |
| 46 | | Crina Anton,
Pierluigi Civera,
Ionel Colonescu,
Enrico Macii,
Massimo Poncino,
Alessandro Bogliolo:
RTL Estimation of Steering Logic Power.
PATMOS 2000: 36-46 |
| 45 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation.
IEEE Design & Test of Computers 17(2): 74-85 (2000) |
| 44 | | Luca Benini,
Giovanni De Micheli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Glitch power minimization by selective gate freezing.
IEEE Trans. VLSI Syst. 8(3): 287-298 (2000) |
| 43 | | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
A multilevel engine for fast power simulation of realistic inputstreams.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 459-472 (2000) |
| 42 | | Fabrizio Ferrandi,
Franco Fummi,
Enrico Macii,
Massimo Poncino,
Donatella Sciuto:
Symbolic optimization of interacting controllers based onredundancy identification and removal.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 760-772 (2000) |
| 41 | | Luca Benini,
Alberto Macii,
Massimo Poncino,
Riccardo Scarsi:
Architectures and synthesis algorithms for power-efficient businterfaces.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 969-980 (2000) |
| 1999 |
|---|
| 40 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses.
DAC 1999: 128-133 |
| 39 | | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms.
DAC 1999: 247-252 |
| 38 | | Luca Benini,
Giovanni De Micheli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Glitch Power Minimization by Gate Freezing.
DATE 1999: 163-167 |
| 37 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems.
EUROMICRO 1999: 1311-1317 |
| 36 | | Alberto Macii,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino,
Riccardo Scarsi:
Regression-Based Macromodeling for Delay Estimation of Behavioral Components.
Great Lakes Symposium on VLSI 1999: 188-191 |
| 35 | | Roberto Corgnati,
Enrico Macii,
Massimo Poncino:
Clustered Table-Based Macromodels for RTL Power Estimation.
Great Lakes Symposium on VLSI 1999: 354-357 |
| 34 | | Alessandro Bogliolo,
Roberto Corgnati,
Enrico Macii,
Massimo Poncino:
Parameterized RTL power models for combinational soft macros.
ICCAD 1999: 284-288 |
| 33 | | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Selective instruction compression for memory energy reduction in embedded systems.
ISLPED 1999: 206-211 |
| 32 | | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.
ACM Trans. Design Autom. Electr. Syst. 4(4): 351-375 (1999) |
| 31 | | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting.
IEEE Trans. Computers 48(8): 769-779 (1999) |
| 1998 |
|---|
| 30 | | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Computational Kernels and their Application to Sequential Power Optimization.
DAC 1998: 764-769 |
| 29 | | Fabrizio Ferrandi,
Franco Fummi,
Enrico Macii,
Massimo Poncino:
Power Estimation of Behavioral Descriptions.
DATE 1998: 762-766 |
| 28 | | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Timed Supersetting and the Synthesis of Telescopic Units.
Great Lakes Symposium on VLSI 1998: 331-337 |
| 27 | | Luca Benini,
Giovanni De Micheli,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.
Great Lakes Symposium on VLSI 1998: 8-12 |
| 26 | | Fabrizio Ferrandi,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi,
Fabio Somenzi:
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits.
ICCAD 1998: 235-241 |
| 25 | | Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Stream synthesis for efficient power simulation based on spectral transforms.
ISLPED 1998: 30-35 |
| 24 | | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Stefano Quer:
Power optimization of core-based systems by address bus encoding.
IEEE Trans. VLSI Syst. 6(4): 554-562 (1998) |
| 23 | | Luca Benini,
Enrico Macii,
Massimo Poncino,
Giovanni De Micheli:
Telescopic units: a new paradigm for performance optimization of VLSI designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 220-232 (1998) |
| 1997 |
|---|
| 22 | | Gianpiero Cabodi,
Paolo Camurati,
Antonio Lioy,
Massimo Poncino,
Stefano Quer:
A parallel approach to symbolic traversal based on set partitioning.
CHARME 1997: 167-184 |
| 21 | | Luca Benini,
Enrico Macii,
Massimo Poncino:
Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control.
DAC 1997: 22-27 |
| 20 | | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.
ED&TC 1997: 514-520 |
| 19 | | Antonio Lioy,
Enrico Macii,
Massimo Poncino,
Massimo Rossello:
Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering.
Great Lakes Symposium on VLSI 1997: 70- |
| 18 | | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Fast power estimation for deterministic input streams.
ICCAD 1997: 494-501 |
| 17 | | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Stefano Quer:
System-level power optimization of special purpose applications: the beach solution.
ISLPED 1997: 24-29 |
| 16 | | Fabrizio Ferrandi,
Franco Fummi,
Donatella Sciuto,
Enrico Macii,
Massimo Poncino:
Testing Core-Based Systems: A Symbolic Methodology.
IEEE Design & Test of Computers 14(4): 69-77 (1997) |
| 1996 |
|---|
| 15 | | Fabrizio Ferrandi,
Franco Fummi,
Enrico Macii,
Massimo Poncino,
Donatella Sciuto:
Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.
DAC 1996: 467-470 |
| 14 | | Enrico Macii,
Massimo Poncino:
Exact Computation of the Entropy of a Logic Circuit.
Great Lakes Symposium on VLSI 1996: 162-167 |
| 13 | | Fabrizio Ferrandi,
Franco Fummi,
Enrico Macii,
Massimo Poncino,
Donatella Sciuto:
Test Generation for Networks of Interacting FSMs Using Symbolic Techniques.
Great Lakes Symposium on VLSI 1996: 208-213 |
| 12 | | Gianpiero Cabodi,
Luciano Lavagno,
Enrico Macii,
Massimo Poncino,
Stefano Quer,
Paolo Camurati,
Ellen Sentovich:
Enhancing FSM Traversal by Temporary Re-Encoding.
ICCD 1996: 6-11 |
| 11 | | Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Massimo Poncino,
Fabio Somenzi:
Automatic state space decomposition for approximate FSM traversal based on circuit analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1451-1464 (1996) |
| 1995 |
|---|
| 10 | | Srilatha Manne,
Abelardo Pardo,
R. Iris Bahar,
Gary D. Hachtel,
Fabio Somenzi,
Enrico Macii,
Massimo Poncino:
Computing the Maximum Power Cycles of a Sequential Circuit.
DAC 1995: 23-28 |
| 9 | | Enrico Macii,
Massimo Poncino:
Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions.
EURO-DAC 1995: 294-299 |
| 8 | | Enrico Macii,
Massimo Poncino:
Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions.
Great Lakes Symposium on VLSI 1995: 112- |
| 7 | | Enrico Macii,
Massimo Poncino:
Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.
Great Lakes Symposium on VLSI 1995: 60-65 |
| 6 | | Enrico Macii,
Massimo Poncino:
Using connectivity and spectral methods to characterize the structure of sequential logic circuits.
Microprocessing and Microprogramming 41(7): 487-500 (1995) |
| 1994 |
|---|
| 5 | | Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Massimo Poncino,
Fabio Somenzi:
A State Space Decomposition Algorithm for Approximate FSM Traversal.
EDAC-ETC-EUROASIC 1994: 137-141 |
| 4 | | Gary D. Hachtel,
Mariano Hermida de la Rica,
Abelardo Pardo,
Massimo Poncino,
Fabio Somenzi:
Re-encoding sequential circuits to reduce power dissipation.
ICCAD 1994: 70-73 |
| 3 | | Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Massimo Poncino,
Fabio Somenzi:
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis.
ICCD 1994: 236-239 |
| 1993 |
|---|
| 2 | | Antonio Lioy,
Massimo Poncino:
On the Resetability of Synchronous Sequential Circuits.
ISCAS 1993: 1507-1510 |
| 1 | | Antonio Lioy,
Massimo Poncino:
A study of the resetability of synchronous sequential circuits.
Microprocessing and Microprogramming 38(1-5): 395-402 (1993) |
