Kishan Prasad

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2006

2 Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar: Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic. ISQED 2006: 617-624

2005

1 Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar: Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits. J. Low Power Electronics 1(2): 182-193 (2005)

	2006
2		Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar: Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic. ISQED 2006: 617-624
	2005
1		Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar: Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits. J. Low Power Electronics 1(2): 182-193 (2005)

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