Serge Pravossoudovitch

2008
60	EE	A. Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, V. Gouin: A Design-for-Diagnosis Technique for SRAM Write Drivers. DATE 2008: 1480-1485
59	EE	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi: SoC Symbolic Simulation: a case study on delay fault testing. DDECS 2008: 320-325
58	EE	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Improving Diagnosis Resolution without Physical Information. DELTA 2008: 210-215
57	EE	A. Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, V. Gouin: An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. VTS 2008: 89-94
2007
56	EE	A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Slow write driver faults in 65nm SRAM technology: analysis and March test solution. DATE 2007: 528-533
55		Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Mixed Approach for Unified Logic Diagnosis. DDECS 2007: 239-242
54	EE	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: DERRIC: A Tool for Unified Logic Diagnosis. European Test Symposium 2007: 13-20
53	EE	O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. European Test Symposium 2007: 77-84
52	EE	A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. European Test Symposium 2007: 97-104
51	EE	A. Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. VTS 2007: 361-368
50	EE	O. Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. VTS 2007: 47-52
49	EE	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. J. Electronic Testing 23(5): 435-444 (2007)
2006
48		Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. DDECS 2006: 256-261
47	EE	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich: Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. VLSI-SoC 2006: 403-408
46	EE	O. Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: An Overview of Failure Mechanisms in Embedded Flash Memories. VTS 2006: 108-113
45	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: A Gated Clock Scheme for Low Power Testing of Logic Cores. J. Electronic Testing 22(1): 89-99 (2006)
44	EE	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing 22(2): 161-172 (2006)
43	EE	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan: ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. J. Electronic Testing 22(3): 287-296 (2006)
2005
42	EE	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. DAC 2005: 857-862
41	EE	Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault: Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. PATMOS 2005: 540-549
40	EE	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault: Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. VLSI-SoC 2005: 267-281
39	EE	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan: Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. VTS 2005: 183-188
38	EE	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electronic Testing 21(1): 43-55 (2005)
37	EE	Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel: Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. J. Electronic Testing 21(2): 169-179 (2005)
36	EE	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan: Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. J. Electronic Testing 21(5): 551-561 (2005)
2004
35	EE	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan: Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. Asian Test Symposium 2004: 266-271
34	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DATE 2004: 62-67
33	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Design of Routing-Constrained Low Power Scan Chains. DELTA 2004: 287-294
32	EE	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA 2004: 83-88
31	EE	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS 2004: 187-192
30	EE	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri: March iC-: An Improved Version of March C- for ADOFs Detection. VTS 2004: 129-138
2003
29	EE	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri: Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. Asian Test Symposium 2003: 250-255
28	EE	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS 2003: 124-128
27	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. ITC 2003: 488-493
2002
26	EE	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Test Power: a Big Issue in Large SOC Designs. DELTA 2002: 447-449
25	EE	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Power Driven Chaining of Flip-Flops in Scan Architectures. ITC 2002: 796-803
24	EE	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: On Using Efficient Test Sequences for BIST. VTS 2002: 145-152
23	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich: High Defect Coverage with Low-Power Test Sequences in a BIST Environment. IEEE Design & Test of Computers 19(5): 44-52 (2002)
2001
22	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Asian Test Symposium 2001: 253-258
21	EE	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Gated Clock Scheme for Low Power Scan-Based BIST. IOLTW 2001: 87-89
20		René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Random Adjacent Sequences: An Efficient Solution for Logic BIST. VLSI-SOC 2001: 413-424
19	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich: A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. VTS 2001: 306-311
2000
18	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: An adjacency-based test pattern generator for low power BIST design. Asian Test Symposium 2000: 459-464
17	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel: Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. IOLTW 2000: 121-126
16		Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch: Low power BIST design by hypergraph partitioning: methodology and architectures. ITC 2000: 652-661
1999
15	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Asian Test Symposium 1999: 89-94
14	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. Great Lakes Symposium on VLSI 1999: 24-
13	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, P. Teixeira, M. Santos: Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113
12	EE	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch: A Test Vector Inhibiting Technique for Low Energy BIST Design. VTS 1999: 407-412
1998
11	EE	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel: A BIST Structure to Test Delay Faults in a Scan Environment. Asian Test Symposium 1998: 435-439
1997
10	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac: A gate resizing technique for high reduction in power consumption. ISLPED 1997: 281-286
9	EE	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch: An optimized BIST test pattern generator for delay testing. VTS 1997: 94-100
8	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac: A non-iterative gate resizing algorithm for high reduction in power consumption. Integration 24(1): 37-52 (1997)
1996
7		Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. ITC 1996: 286-293
6	EE	S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: A new test pattern generation method for delay fault testing. VTS 1996: 296-301
1995
5	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez: Diagnostic of path and gate delay faults in non-scan sequential circuits. VTS 1995: 380-386
1994
4		D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. EDAC-ETC-EUROASIC 1994: 518-523
1993
3		D. Dumas, Patrick Girard, Christian Landrault, Serge Pravossoudovitch: An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. ITC 1993: 705-713
1992
2	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch: A Novel Approach to Delay-Fault Diagnosis. DAC 1992: 357-360
1	EE	Patrick Girard, Christian Landrault, Serge Pravossoudovitch: Delay-Fault Diagnosis by Critical-Path Tracing. IEEE Design & Test of Computers 9(4): 27-32 (1992)

Coauthor Index

1	Nabil Badereddine	[40] [41] [47]
2	Magali Bastian	[42] [48] [49] [51] [52] [56] [57] [60]
3	Paolo Bernardi	[59]
4	Yannick Bonhomme	[21] [22] [25] [26] [27] [33] [34] [45]
5	Simone Borri	[29] [30] [35] [36] [37] [43]
6	Alberto Bosio	[54] [55] [58] [59]
7	Marylene Combe	[46]
8	S. Cremoux	[6]
9	Jean Michel Daga	[46] [50] [53]
10	René David	[20] [24]
11	Luigi Dilillo	[29] [30] [35] [36] [37] [39] [42] [43] [48] [49]
12	D. Dumas	[3] [4]
13	Christophe Fagot	[6]
14	Joan Figueras	[13]
15	O. Ginez	[46] [50] [53]
16	Patrick Girard	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [43] [44] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [59] [60]
17	V. Gouin	[57] [60]
18	Loïs Guiller	[12] [13] [14] [15] [16] [18] [19] [21] [22] [27] [33] [34] [45]
19	Magali Bastian Hage-Hassan	[35] [36] [37] [39] [43]
20	Olivier Héron	[28] [31] [32] [38] [44]
21	Christian Landrault	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [33] [34] [40] [41] [45] [46] [47] [50] [51] [52] [53] [54] [55] [56] [58]
22	Salvador Manich	[13]
23	V. Moreda	[9] [11]
24	A. Ney	[51] [52] [56] [57] [60]
25	Michel Renovell	[28] [31] [32] [38] [44]
26	B. Rodriguez	[5] [7]
27	Alexandre Rousset	[54] [55] [58]
28	M. Santos	[13]
29	D. Severac	[8] [10]
30	P. Teixeira	[13]
31	Arnaud Virazel	[11] [17] [20] [23] [24] [29] [30] [33] [34] [35] [36] [37] [39] [40] [41] [42] [43] [45] [46] [47] [48] [49] [50] [51] [52] [53] [54] [55] [56] [57] [58] [60]
32	Hans-Joachim Wunderlich	[19] [23] [47]