Antonio Pullini

	2009
12		Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii: Physically clustered forward body biasing for variability compensation in nanometer CMOS design. DATE 2009: 154-159
11		Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli: Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. DATE 2009: 616-621
	2008
10		Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Optimal sleep transistor synthesis under timing and area constraints. ACM Great Lakes Symposium on VLSI 2008: 177-182
9		Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: A Scalable Algorithmic Framework for Row-Based Power-Gating. DATE 2008: 379-384
8		Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. ISCAS 2008: 2761-2764
7		David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli: Network-on-Chip design and synthesis outlook. Integration 41(3): 340-359 (2008)
	2007
6		Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. ACM Great Lakes Symposium on VLSI 2007: 501-504
5		Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino: Timing-driven row-based power gating. ISLPED 2007: 104-109
4		Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini: NoC Design and Implementation in 65nm Technology. NOCS 2007: 273-282
3		Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini: Bringing NoCs to 65 nm. IEEE Micro 27(5): 75-85 (2007)
2		Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli: Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1297-1310 (2007)
	2005
1		Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini: Fault tolerance overhead in network-on-chip flow control schemes. SBCCI 2005: 224-229

Coauthor Index

1	Federico Angiolini	[1] [2] [3] [4] [7]
2	David Atienza	[3] [4] [7] [11]
3	Luca Benini	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12]
4	Davide Bertozzi	[1]
5	Shashikanth Bobba	[11]
6	Andrea Calimera	[6] [8]
7	Alberto Macii	[5] [6] [8] [9] [10]
8	Enrico Macii	[5] [6] [8] [9] [10] [12]
9	Paolo Meloni	[4]
10	Giovanni De Micheli	[2] [3] [4] [7] [11] [12]
11	Srinivasan Murali	[2] [3] [4] [7]
12	Massimo Poncino	[5] [6] [8] [9] [10]
13	Luigi Raffo	[4]
14	Ashoka Visweswara Sathanur	[5] [6] [8] [9] [10] [12]
15	Stergios Stergiou	[2]
16	Rutuparna Tamhankar	[2]
17	Jie Zhang	[11]