Hafizur Rahaman

	2009
26		Tuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta: A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. VLSI Design 2009: 387-392
	2008
25		Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta: Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. ISVLSI 2008: 369-374
24		Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: Revisiting fidelity: a case of elmore-based Y-routing trees. SLIP 2008: 27-34
23		Hafizur Rahaman, Dipak K. Kole, Debesh Kumar Das, Bhargab B. Bhattacharya: On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. VLSI Design 2008: 163-168
22		Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan: Single Error Correcting Finite Field Multipliers Over GF(2m). VLSI Design 2008: 33-38
21		Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan: Design of Reversible Finite Field Arithmetic Circuits with Error Detection. VLSI Design 2008: 453-459
20		Jimson Mathew, Hafizur Rahaman, A. K. Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan: A Galois Field Based Logic Synthesis Approach with Testability. VLSI Design 2008: 629-634
19		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: C-testable bit parallel multipliers over GF(2m). ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
18		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). IEEE Trans. Computers 57(9): 1289-1294 (2008)
	2007
17		Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan: Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. IOLTS 2007: 207-208
16		Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: Minimum-Congestion Placement for Y-interconnects: Some studies and observations. ISVLSI 2007: 73-80
15		Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan: Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). VLSI Design 2007: 479-484
14		Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan: Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430
	2006
13		Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta: A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI. ISCAS 2006
12		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. J. Electronic Testing 22(2): 125-142 (2006)
11		Susmit Bagchi, Hafizur Rahaman, Purnendu Das: MDVM System Concept, Paging Latency and Round-2 Randomized Leader Election Algorithm in SG. JACIII 10(5): 752-760 (2006)
	2005
10		Hafizur Rahaman, Debesh K. Das: Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. ASP-DAC 2005: 172-177
9		Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar: Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. Asian Test Symposium 2005: 284-287
8		Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta: Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design. IICAI 2005: 232-251
	2004
7		Hafizur Rahaman, Debesh K. Das: A Simple Delay Testable Synthesis of Symmetric Functions. AACC 2004: 263-270
6		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. ASP-DAC 2004: 224-229
5		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. VLSI Design 2004: 487-492
	2003
4		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. Asian Test Symposium 2003: 284-289
	2002
3		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: A New Synthesis of Symmetric Functions. VLSI Design 2002: 160-165
2		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. J. Comput. Sci. Technol. 17(6): 731-737 (2002)
	1999
1		Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya: An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. ASP-DAC 1999: 287-

Coauthor Index

1	Costas Argyrides	[22]
2	Susmit Bagchi	[11]
3	Bhargab B. Bhattacharya	[1] [2] [3] [4] [5] [6] [12] [23]
4	Debesh Kumar Das (Debesh K. Das)	[1] [2] [3] [4] [5] [6] [7] [10] [12] [23]
5	Purnendu Das	[11]
6	Sukanta Das	[9]
7	Parthasarathi Dasgupta (P. S. Dasgupta)	[8] [13] [16] [24] [25] [26]
8	Prasun Ghosal	[8] [13] [16] [24] [25] [26]
9	Abusaleh M. Jabir	[18] [19] [20] [22]
10	Babita R. Jose	[21]
11	Dipak K. Kole	[23]
12	Jimson Mathew	[14] [15] [17] [18] [19] [20] [21] [22]
13	Dhiraj K. Pradhan	[14] [15] [17] [18] [19] [20] [21] [22]
14	Tuhina Samanta	[8] [13] [16] [24] [25] [26]
15	Biplab K. Sikdar	[9] [14]
16	A. K. Singh	[20]

Colors in the list of coauthors