Jaan Raik

2008
27	EE	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Parallel fault backtracing for calculation of fault coverage. ASP-DAC 2008: 667-672
26	EE	Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee: Code Coverage Analysis using High-Level Decision Diagrams. DDECS 2008: 201-206
25	EE	Eero Ivask, Jaan Raik, Raimund Ubar: Web-Based Framework for Parallel Distributed Test. DDECS 2008: 271-274
24	EE	Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee: Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA 2008: 222-227
2007
23		Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski: Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS 2007: 35-40
22	EE	Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen: Fault Diagnosis in Integrated Circuits with BIST. DSD 2007: 604-610
21	EE	Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus: Hierarchical Identification of Untestable Faults in Sequential Circuits. DSD 2007: 668-671
20	EE	Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman: Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. European Test Symposium 2007: 131-136
19	EE	Jaan Raik, Raimund Ubar, Vineeth Govind: Test Configurations for Diagnosing Faulty Links in NoC Switches. European Test Symposium 2007: 29-34
2006
18	EE	Jaan Raik, Raimund Ubar, Taavi Viilukas: High-Level Decision Diagram based Fault Models for Targeting FSMs. DSD 2006: 353-358
2005
17	EE	Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov: An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. DSD 2005: 412-419
16	EE	Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar: Improved Fault Emulation for Synchronous Sequential Circuits. DSD 2005: 72-78
15	EE	Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz: Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD 2005: 79-82
14	EE	Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman: Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC 2005: 332-344
13	EE	Jaan Raik, Tanel Nõmmeots, Raimund Ubar: A New Testability Calculation Method to Guide RTL Test Generation. J. Electronic Testing 21(1): 71-82 (2005)
2004
12	EE	Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe: Evaluating Fault Emulation on FPGA. FPL 2004: 354-363
11		Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider: Web-Based Environment for Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks 2004: 435-442
2002
10	EE	André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová: Internet-Based Collaborative Test Generation with MOSCITO. DATE 2002: 221-226
9	EE	Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik: Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. DELTA 2002: 86-91
8	EE	T. Cibáková, María Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Hierarchical test generation for combinational circuits with real defects coverage. Microelectronics Reliability 42(7): 1141-1149 (2002)
2001
7	EE	Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED 2001: 365-371
6	EE	Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar: Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectronics Reliability 41(12): 2023-2040 (2001)
2000
5	EE	Adam Morawiec, Raimund Ubar, Jaan Raik: Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. DATE 2000: 743
4	EE	Raimund Ubar, Jaan Raik: Efficient Hierarchical Approach to Test Generation for Digital Systems. ISQED 2000: 189-196
1999
3	EE	Raimund Ubar, Jaan Raik, Adam Morawiec: Cycle-based Simulation with Decision Diagrams. DATE 1999: 454-458
2	EE	Jaan Raik, Raimund Ubar: Sequential Circuit Test Generation Using Decision Diagram Models. DATE 1999: 736-740
1997
1	EE	Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar: Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217

Coauthor Index

1	Alfredo Benso	[1]
2	Mykola Blyzniuk	[6]
3	Marina Brik	[9]
4	T. Cibáková	[8] [10]
5	Sergei Devadze	[14] [20] [24] [27]
6	Karl-Heinz Diener	[10]
7	Peeter Ellervee	[12] [16] [24] [26]
8	Teet Evartson	[22]
9	María Fischerová	[8]
10	Vineeth Govind	[19]
11	Elena Gramatová	[8] [10]
12	Eero Ivask	[9] [10] [11] [25]
13	Maksim Jenihhin	[23] [24] [26]
14	Gert Jervan	[24]
15	Artur Jutman	[14] [17] [20] [27]
16	Irena Kazymyra	[6]
17	Sergei Kostin	[22]
18	Anna Krivenko	[21]
19	Margus Kruus	[21]
20	Wieslaw Kuzmicz	[6] [7] [8] [15]
21	Harri Lensen	[22]
22	P. Miklos	[10]
23	Adam Morawiec	[3] [5]
24	Tanel Nõmmeots	[13]
25	Witold A. Pleskacz	[6] [7] [8] [15] [23]
26	Paolo Prinetto	[1]
27	Michal Rakowski	[23]
28	Maurizio Rebaudengo	[1]
29	Uljana Reinsalu	[26]
30	Matteo Sonza Reorda	[1]
31	André Schneider	[10] [11]
32	Joachim Sudbrock	[15]
33	Kalle Tammemäe	[12]
34	Valentin Tihhomirov	[12] [16]
35	Raimund Ubar	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27]
36	Taavi Viilukas	[18]
37	V. Vislogubov	[17]