 | 2008 |
|---|
| 8 |       | Sridhar Rajagopal,
Joseph R. Cavallaro:
Communication Processors for Wireless Systems.
Wiley Encyclopedia of Computer Science and Engineering 2008 |
| 2006 |
|---|
| 7 | | Sridhar Rajagopal,
Joseph R. Cavallaro:
Truncated Online Arithmetic with Applications to Communication Systems.
IEEE Trans. Computers 55(10): 1240-12529 (2006) |
| 2004 |
|---|
| 6 | | Sridhar Rajagopal,
Joseph R. Cavallaro,
Scott Rixner:
Design Space Exploration for Real-Time Embedded Stream Processors.
IEEE Micro 24(4): 54-66 (2004) |
| 2002 |
|---|
| 5 | | Gang Xu,
Sridhar Rajagopal,
Joseph R. Cavallaro,
Behnaam Aazhang:
VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers.
VLSI Signal Processing 30(1-3): 21-33 (2002) |
| 4 | | Sridhar Rajagopal,
Srikrishna Bhashyam,
Joseph R. Cavallaro,
Behnaam Aazhang:
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers.
VLSI Signal Processing 31(2): 143-156 (2002) |
| 2001 |
|---|
| 3 | | Sridhar Rajagopal,
Joseph R. Cavallaro:
On-line Arithmetic for Detection in Digital Communication Receivers.
IEEE Symposium on Computer Arithmetic 2001: 257-265 |
| 2 | | Sridhar Rajagopal,
Joseph R. Cavallaro:
A bit-streaming, pipelined multiuser detector for wireless communication receivers.
ISCAS (4) 2001: 128-131 |
| 2000 |
|---|
| 1 | | Sridhar Rajagopal,
Srikrishna Bhashyam,
Joseph R. Cavallaro,
Behnaam Aazhang:
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers.
ASAP 2000: 173-184 |
