Anand Rajaram Coauthor index DBLP Vis pubzone.org

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DBLP keys2009
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAshutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan: Analysis and optimization of NBTI induced clock skew in gated clock trees. DATE 2009: 296-299
2008
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, David Z. Pan: MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. ASP-DAC 2008: 250-257
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, David Z. Pan: Robust chip-level clock tree synthesis for SOC designs. DAC 2008: 720-723
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, Raguram Damodaran, Arjun Rajagopal: Practical Clock Tree Robustness Signoff Metrics. ISQED 2008: 676-679
2007
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJoon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan: Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. ISQED 2007: 398-403
2006
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, David Z. Pan: Variation tolerant buffered clock network synthesis with cross links. ISPD 2006: 157-164
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, David Z. Pan: Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. ISQED 2006: 79-84
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, Jiang Hu, Rabi N. Mahapatra: Reducing clock skew variability via crosslinks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1176-1182 (2006)
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo: Analytical bound for unwanted clock skew due to wire width variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1869-1876 (2006)
2005
4no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGanesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert: Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD 2005: 592-596
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, David Z. Pan, Jiang Hu: Improved algorithms for link-based non-tree clock networks for skew variability reduction. ISPD 2005: 55-62
2004
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, Jiang Hu, Rabi N. Mahapatra: Reducing clock skew variability via cross links. DAC 2004: 18-23
2003
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu: Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. ICCAD 2003: 401-407

Coauthor Index

1Charles J. Alpert [4]
2Ashutosh Chakraborty [13]
3Jian Chen [9]
4Raguram Damodaran [10]
5Gokul Ganesan [13]
6Wei Guo [1] [5]
7Jiang Hu [1] [2] [3] [4] [5] [6]
8Nikhil Jayakumar [4]
9Sunil P. Khatri [4]
10Peng Li [4]
11Bing Lu [1] [5]
12Rabi N. Mahapatra [1] [2] [5] [6]
13Patrick McGuinness [4]
14David Z. Pan (David Zhigang Pan) [3] [7] [8] [9] [11] [12] [13]
15Arjun Rajagopal [10]
16Ninghy Shi [9]
17Ganesh Venkataraman [4]
18Joon-Sung Yang [9]

Colors in the list of coauthors

Copyright © Tue Dec 1 12:01:14 2009 by Michael Ley (ley@uni-trier.de)