Rahul M. Rao

	2011
18		Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang: SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Trans. VLSI Syst. 19(1): 24-32 (2011)
	2010
17		Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim: Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. CICC 2010: 1-4
16		Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown: Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise. IEEE Trans. VLSI Syst. 18(1): 166-170 (2010)
	2009
15		Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang: A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. ISCAS 2009: 381-384
14		Amlan Ghosh, Rahul M. Rao, Richard B. Brown: A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. ISLPED 2009: 45-50
13		Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang: Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectronics Reliability 49(6): 642-649 (2009)
	2008
12		Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang: Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS 2008: 384-387
11		Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown: On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. ISQED 2008: 815-820
10		Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown: On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design 2008: 143-149
	2007
9		Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. VLSI Syst. 15(6): 613-623 (2007)
	2005
8		Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif: Power-aware global signaling strategies. ISCAS (1) 2005: 604-607
7		Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290
6		Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka: Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. ISQED 2005: 88-93
	2004
5		Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif: Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193
4		Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown: Analysis and Optimization of Enhanced MTCMOS Scheme. VLSI Design 2004: 234-239
	2003
3		Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown: A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD 2003: 689-692
2		Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown: Efficient techniques for gate leakage estimation. ISLPED 2003: 100-103
1		Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns: Leakage and leakage sensitivity computation for combinational circuits. ISLPED 2003: 96-99

Coauthor Index

1	Emrah Acar	[1]
2	Kanak Agarwal	[5] [7] [8] [9] [16]
3	Aditya Bansal	[13]
4	Richard B. Brown	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [14] [15] [16]
5	Jeffrey L. Burns	[1] [2] [3] [4]
6	Ching-Te Chuang	[10] [11] [12] [13] [15] [18]
7	Harmander Deogun	[6]
8	Anirudh Devgan	[1] [2] [7]
9	Amlan Ghosh	[10] [11] [14] [15]
10	Himanshu Kaul	[8]
11	Jae-Joon Kim	[10] [12] [13] [17] [18]
12	Keunwoo Kim	[17]
13	Frank Liu	[3]
14	Ying Liu	[1]
15	Saibal Mukhopadhyay	[12] [18]
16	Sani R. Nassif	[1] [5] [8]
17	Kevin J. Nowka	[5] [6] [7]
18	Harmander Singh	[16]
19	James H. Stathis	[13]
20	Haihua Su	[1]
21	Dennis Sylvester	[5] [6] [7] [8] [9] [16]
22	Sufi Zafar	[13]

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