 | 2007 |
| 13 |  | Rajeev R. Rao,
Kaviraj Chopra,
David T. Blaauw,
Dennis Sylvester:
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007) |
| 2006 |
| 12 |  | Rajeev R. Rao,
Kaviraj Chopra,
David Blaauw,
Dennis Sylvester:
An efficient static algorithm for computing the soft error rates of combinational circuits.
DATE 2006: 164-169 |
| 11 |  | Rajeev R. Rao,
David Blaauw,
Dennis Sylvester:
Soft error reduction in combinational logic using gate resizing and flipflop selection.
ICCAD 2006: 502-509 |
| 10 |  | Vivek Joshi,
Rajeev R. Rao,
David Blaauw,
Dennis Sylvester:
Logic SER Reduction through Flipflop Redesign.
ISQED 2006: 611-616 |
| 9 |  | Rajeev R. Rao,
Anirudh Devgan,
David Blaauw,
Dennis Sylvester:
Analytical yield prediction considering leakage/performance correlation.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006) |
| 2005 |
| 8 |  | Rajeev R. Rao,
David Blaauw,
Dennis Sylvester,
Charles J. Alpert,
Sani R. Nassif:
An efficient surface-based low-power buffer insertion algorithm.
ISPD 2005: 86-93 |
| 7 |  | Rajeev R. Rao,
David Blaauw,
Dennis Sylvester,
Anirudh Devgan:
Modeling and Analysis of Parametric Yield under Power and Performance Constraints.
IEEE Design & Test of Computers 22(4): 376-385 (2005) |
| 6 |  | Rajeev R. Rao,
Harmander Deogun,
David Blaauw,
Dennis Sylvester:
Bus encoding for total power reduction using a leakage-aware buffer configuration.
IEEE Trans. VLSI Syst. 13(12): 1376-1383 (2005) |
| 2004 |
| 5 |  | Rajeev R. Rao,
Anirudh Devgan,
David Blaauw,
Dennis Sylvester:
Parametric yield estimation considering leakage variability.
DAC 2004: 442-447 |
| 4 |  | Harmander Deogun,
Rajeev R. Rao,
Dennis Sylvester,
David Blaauw:
Leakage-and crosstalk-aware bus encoding for total power reduction.
DAC 2004: 779-782 |
| 3 |  | Rajeev R. Rao,
Ashish Srivastava,
David Blaauw,
Dennis Sylvester:
Statistical analysis of subthreshold leakage current for VLSI circuits.
IEEE Trans. VLSI Syst. 12(2): 131-139 (2004) |
| 2003 |
| 2 |  | Rajeev R. Rao,
Ashish Srivastava,
David Blaauw,
Dennis Sylvester:
Statistical estimation of leakage current considering inter- and intra-die process variation.
ISLPED 2003: 84-89 |
| 1 |  | Dan Ernst,
Nam Sung Kim,
Shidhartha Das,
Sanjay Pant,
Rajeev R. Rao,
Toan Pham,
Conrad H. Ziesler,
David Blaauw,
Todd M. Austin,
Krisztián Flautner,
Trevor N. Mudge:
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.
MICRO 2003: 7-18 |