V. Ramgopal Rao

	2009
12		Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil: Automated design and optimization of circuits in emerging technologies. ASP-DAC 2009: 504-509
	2007
11		Yusuke Kobayashi, C. Raghunathan Manoj, Kazuo Tsutsui, Venkanarayan Hariharan, Kuniyuki Kakushima, V. Ramgopal Rao, Parhat Ahmet, Hiroshi Iwai: Parasitic Effects in Multi-Gate MOSFETs. IEICE Transactions 90-C(10): 2051-2056 (2007)
	2006
10		K. Narasimhulu, V. Ramgopal Rao: Embedded Tutorial: Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies. VLSI Design 2006: 45-50
	2004
9		K. Narasimhulu, Siva Narendra, V. Ramgopal Rao: The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance. VLSI Design 2004: 545-550
	2003
8		Najeebuddin Hakim, V. Ramgopal Rao, J. Vasi: Small Signal Characteristics of Thin Film Single Halo SOI MOSFET for Mixed Mode Applications. VLSI Design 2003: 110-115
7		D. Vinay Kumar, Nihar R. Mohapatra, Mahesh B. Patil, V. Ramgopal Rao: Application of Look-up Table Approach to High-K Gate Dielectric MOS Transistor circuits. VLSI Design 2003: 128-
6		Abhisek Dixit, V. Ramgopal Rao: A Novel Dynamic Threshold Operation Using Electrically Induced Junction MOSFET in the Deep Sub-micrometer CMOS Regime. VLSI Design 2003: 499-503
5		Nihar R. Mohapatra, Madhav P. Desai, V. Ramgopal Rao: Detailed Analysis of FIBL in MOS Transistors with High-K Gate Dielectrics. VLSI Design 2003: 99-104
	2001
4		G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, Walter Hansch, I. Eisele: erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering. VLSI Design 2001: 475-478
3		Nihar R. Mohapatra, A. Dutta, Madhav P. Desai, V. Ramgopal Rao: Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. VLSI Design 2001: 479-
2		Nihar R. Mohapatra, A. Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao: Sub-100 nm CMOS circuit performance with high-K gate dielectrics. Microelectronics Reliability 41(7): 1045-1048 (2001)
1		A. Kumar, S. Mahapatra, R. Lal, V. Ramgopal Rao: Multi-frequency transconductance technique for interface characterization of deep sub-micron SOI-MOSFETs. Microelectronics Reliability 41(7): 1049-1051 (2001)

Coauthor Index

1	Parhat Ahmet	[11]
2	K. G. Anil	[4]
3	Maryam Shojaei Baghini	[12]
4	Madhav P. Desai	[2] [3] [5]
5	Abhisek Dixit	[6]
6	A. Dutta	[2] [3]
7	I. Eisele	[4]
8	C. Fink	[4]
9	Najeebuddin Hakim	[8]
10	Walter Hansch	[4]
11	Venkanarayan Hariharan	[11]
12	Hiroshi Iwai	[11]
13	Kuniyuki Kakushima	[11]
14	Yusuke Kobayashi	[11]
15	A. Kumar	[1]
16	D. Vinay Kumar	[7]
17	R. Lal	[1]
18	S. Mahapatra	[1] [4]
19	C. Raghunathan Manoj	[11]
20	Nihar R. Mohapatra	[2] [3] [5] [7]
21	K. Narasimhulu	[9] [10]
22	Siva Narendra	[9]
23	Mahesh B. Patil	[7] [12]
24	Angada B. Sachid	[12]
25	Chaitanya Sathe	[12]
26	G. Shrivastav	[4]
27	G. Sridhar	[2]
28	Rajesh Amratlal Thakker	[12]
29	Kazuo Tsutsui	[11]
30	J. Vasi	[4] [8]

Colors in the list of coauthors