Vasant B. Rao

	2002
14		Vasant B. Rao, Jeffrey Soreff, Ravichander Ledalla, Fred L. Yang: Aggressive crunching of extracted RC netlists. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 70-77
	1996
13		John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit DasGupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang: Design planning for high-performance ASICs. IBM Journal of Research and Development 40(4): 431-452 (1996)
	1995
12		Vasant B. Rao: Delay Analysis of the Distributed RC Line. DAC 1995: 370-375
	1993
11		Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang: An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1621-1634 (1993)
	1991
10		Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya: A Convex Optimization Approach to Transistor Sizing for CMOS Circuits. ICCAD 1991: 482-485
9		Youssef Saab, Vasant B. Rao: Combinatorial optimization by stochastic evolution. IEEE Trans. on CAD of Integrated Circuits and Systems 10(4): 525-535 (1991)
8		Yun-Cheng Ju, Vasant B. Rao, Resve A. Saleh: Consistency checking and optimization of macromodels. IEEE Trans. on CAD of Integrated Circuits and Systems 10(8): 957-967 (1991)
	1990
7		Youssef Saab, Vasant B. Rao: Stochastic Evolution: a Fast Effective Heuristic for Some Generic Layout Problems. DAC 1990: 26-31
6		Youssef Saab, Vasant B. Rao: Fast effective heuristics for the graph bisectioning problem. IEEE Trans. on CAD of Integrated Circuits and Systems 9(1): 91-98 (1990)
	1989
5		Youssef Saab, Vasant B. Rao: An Evolution-Based Approach to Partitioning ASIC Systems. DAC 1989: 767-770
4		Youssef Saab, Vasant B. Rao: A Stochastic Algorithm for Circuit Bi-Partitioning. Great Lakes Computer Science Conference 1989: 313-321
	1988
3		M. A. Manzoul, Vasant B. Rao: Multi-Input Fuzzy Inference Engine on a Systolic Array. IEA/AIE (Vol. 2) 1988: 958-964
	1987
2		Shun-Lin Su, Vasant B. Rao, Timothy N. Trick: HPEX: A Hierarchical Parasitic Circuit Extractor. DAC 1987: 566-569
1		Vasant B. Rao, Timothy N. Trick: Network Partitioning and Ordering for MOS VLSI Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 6(1): 128-144 (1987)

Coauthor Index

1	Jitendra M. Apte	[13]
2	S. Wayne Bollinger	[13]
3	Hai Hsia Chen	[13]
4	Sumit DasGupta	[13]
5	Rajesh K. Gupta (Rajesh Gupta)	[13]
6	Philip S. Honsinger	[13]
7	Edward P. Hsieh	[13]
8	Andrew D. Huber	[13]
9	Edward J. Hughes	[13]
10	Yun-Cheng Ju	[8]
11	Sung-Mo Kang	[11]
12	Zahi M. Kurzum	[13]
13	Ravichander Ledalla	[14]
14	M. A. Manzoul	[3]
15	Youssef Saab	[4] [5] [6] [7] [9]
16	Resve A. Saleh (Resve Saleh, Res Saleh)	[8]
17	Sachin S. Sapatnekar	[10] [11]
18	John Y. Sayah	[13]
19	Deepak D. Sherlekar	[13]
20	Jeffrey Soreff	[14]
21	Shun-Lin Su	[2]
22	Thepthai Tabtieng	[13]
23	Timothy N. Trick	[1] [2]
24	Pravin M. Vaidya	[10] [11]
25	Vigen Valijan	[13]
26	David Y. Yang	[13]
27	Fred L. Yang	[14]

Colors in the list of coauthors