C. P. Ravikumar

	2008
81		Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle: Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008 ACM 2008
80		C. P. Ravikumar, M. Hirech, X. Wen: Test Strategies for Low Power Devices. DATE 2008: 728-733
79		Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan: Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. VLSI Design 2008: 169-174
78		T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan: Memory Architecture Exploration Framework for Cache Based Embedded SOC. VLSI Design 2008: 553-559
	2007
77		T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan: MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. ASP-DAC 2007: 492-497
76		V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE 2007: 534-539
75		V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design 2007: 351-356
74		T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan: MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. VLSI Design 2007: 527-533
73		V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS 2007: 167-172
72		Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar: A critical-path-aware partial gating approach for test power reduction. ACM Trans. Design Autom. Electr. Syst. 12(2): (2007)
71		C. P. Ravikumar, Jari Nurmi: Conference Reports. IEEE Design & Test of Computers 24(2): 202-203 (2007)
70		V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: Variation-Tolerant, Power-Safe Pattern Generation. IEEE Design & Test of Computers 24(4): 374-384 (2007)
69		Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler: Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 896-906 (2007)
68		Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy: Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electronics 3(1): 106-118 (2007)
	2006
67		Mitra Subhasish, Ondrej Novák, Hana Kubatova, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar: Conference Reports. IEEE Design & Test of Computers 23(4): 262-265 (2006)
66		V. R. Devanathan, C. P. Ravikumar, V. Kamakoti: On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electronics 2(3): 464-476 (2006)
	2005
65		Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar: Partial Gating Optimization for Power Reduction During Test Application. Asian Test Symposium 2005: 242-247
64		C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar: A Framework for Distributed and Hierarchical Design-for-Test. VLSI Design 2005: 497-503
63		Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic: At-Speed Transition Fault Testing With Low Speed Scan Enable. VTS 2005: 42-47
	2004
62		C. P. Ravikumar, Graham Hetherington: A Holistic Parallel and Hierarchical Approach towards Design-For-Test. ITC 2004: 345-354
61		C. P. Ravikumar: Multiprocessor Architectures for Embedded System-on-chip Applications. VLSI Design 2004: 512-519
60		Aman Kokrady, C. P. Ravikumar: Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. VLSI Design 2004: 597-
59		Mohammed Fadle Abdulla, C. P. Ravikumar: A self-checking signature scheme for checking backdoor security attacks in Internet. J. High Speed Networks 13(4): 309-317 (2004)
	2003
58		Aman Kokrady, C. P. Ravikumar: Static Verification of Test Vectors for IR Drop Failure. ICCAD 2003: 760-764
57		C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra: Mutual Testing based on Wavelet Transforms. VLSI Design 2003: 347-352
	2002
56		Mirza Mohd. Sufyan Beg, C. P. Ravikumar: Measuring the Quality of Web Search Results. JCIS 2002: 324-328
55		Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri: Improvement of ASIC Design Processes. VLSI Design 2002: 105-
54		S. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri: An Evolutionary Scheme for Cosynthesis of Real-Time Systems. VLSI Design 2002: 251-
53		Rahul Kumar, C. P. Ravikumar: Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. VLSI Design 2002: 45-50
52		C. P. Ravikumar, Rahul Kumar: Divide-and-Conquer IDDQ Testing for Core-Based System Chips. VLSI Design 2002: 761-766
	2001
51		Vishal Dalal, C. P. Ravikumar: Software Power Optimizations In An Embedded System. VLSI Design 2001: 254-
50		V. Sankara Subramanian, C. P. Ravikumar: Estimating Crosstalk From Vlsi Layouts. VLSI Design 2001: 531-
49		Vineet Sahula, C. P. Ravikumar: The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes. VLSI Design 2001: 91-96
	2000
48		Rajesh Kannah, C. P. Ravikumar: Functional Testing of Microprocessors with Graded Fault Coverage. Asian Test Symposium 2000: 204-
47		S. Chakraverty, C. P. Ravikumar: A Stochastic Framework for Co-synthesis of Real-Time Systems. LCTES 2000: 96-113
46		Anil Sharma, C. P. Ravikumar: Efficient Implementation of ADPCM Codec. VLSI Design 2000: 456-461
45		C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma: Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. VLSI Design 2000: 462-467
44		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: A scheme for multiple on-chip signature checking for embedded SRAMS. Journal of Systems Architecture 46(2): 181-199 (2000)
	1999
43		C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra: A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems. Asian Test Symposium 1999: 107-112
42		Rohit Sharma, C. P. Ravikumar: Design Issues in Synthesis of Reusable Cores. Great Lakes Symposium on VLSI 1999: 144-
41		Nishit Narang, Girish Kumar, C. P. Ravikumar: Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications. HiPC 1999: 169-173
40		C. P. Ravikumar, Meeta Sharma, Prachi Jain: Design of WDM Networks for Delay-Bound Multicasting. HiPC 1999: 399-403
39		C. P. Ravikumar, Manish Sharma, R. K. Patney: Improving the Diagnosability of Digital Circuits. VLSI Design 1999: 629-634
38		C. P. Ravikumar, Ajay Mittal: Hierarchical Delay Fault Simulation. VLSI Design 1999: 635-
37		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: Built-in Self Test Based on Multiple On-Chip Signature Checking. J. Electronic Testing 14(3): 227-244 (1999)
	1998
36		C. P. Ravikumar, N. Satya Prasad: Evaluating BIST Architectures for Low Power. Asian Test Symposium 1998: 430-434
35		Nidhi Agrawal, C. P. Ravikumar: Adaptive Routing Based on Deadlock Recovery. Euro-Par 1998: 981-988
34		C. P. Ravikumar, Sumit Gupta, Akshay Jajoo: Synthesis of Testable RTL Designs. VLSI Design 1998: 187-192
33		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: Hybrid Testing Schemes Based on Mutual and Signature Testing. VLSI Design 1998: 293-
32		Suhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar: Freedom: Statistical Behavioral Estimation of System Energy and Power. VLSI Design 1998: 30-36
31		Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar: An Evolutionary Approach to System Redesign. VLSI Design 1998: 359-
30		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: On-Chip Signature Checking for Embedded Memories. VLSI Design 1998: 558-563
29		C. P. Ravikumar, Rajneesh Bajpai: Source-based delay-bounded multicasting in multimedia networks. Computer Communications 21(2): 126-132 (1998)
28		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. J. Electronic Testing 12(3): 199-216 (1998)
	1997
27		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: A scheme for multiple on-chip signature checking for embedded SRAMs. ED&TC 1997: 625
26		Nidhi Agrawal, C. P. Ravikumar: An Euler Path Based Technique for Deadlock-free Multicasting. ICPP 1997: 378-384
25		C. P. Ravikumar, R. Aggarwal, C. Sharma: A Graph-Theoretic Approach for Register File Based Synthesis. VLSI Design 1997: 118-123
24		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: Efficient Implementation of Multiple On-Chip Signature Checking. VLSI Design 1997: 297-302
23		C. P. Ravikumar, Vikas Jain, Anurag Dod: Faster Fault Simulation Through Distributed Computing. VLSI Design 1997: 482-487
22		Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar: Rapid Synthesis of Multi-Chip Systems. VLSI Design 1997: 62-68
21		C. P. Ravikumar, Tarun Rai, Varun Verma: Kautz graphs as attractive logical topologies in multihop lightwave networks. Computer Communications 20(14): 1259-1270 (1997)
20		C. P. Ravikumar, Nitin Agrawal, Parul Agarwal: Hierarchical Delay Test Generation. J. Electronic Testing 10(3): 231-244 (1997)
	1996
19		Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar: Efficient Delay Test Generation for Modular Circuits. Great Lakes Symposium on VLSI 1996: 220-
18		C. P. Ravikumar, Rajamani Rajarajan: Genetic Algorithms for Scan Path Design. VLSI Design 1996: 118-121
17		C. P. Ravikumar, V. Saxena: Synthesis of Testable Pipelined Datapaths Using Genetic Search. VLSI Design 1996: 205-210
16		C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora: Estimation of Power from Module-level Netlists. VLSI Design 1996: 324-325
15		Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar: A Novel BIST Architecture With Built-in Self Check. VLSI Design 1996: 57-60
14		Nidhi Agrawal, C. P. Ravikumar: Fault-tolerant routing in multiply twisted cube topology. Journal of Systems Architecture 42(4): 279-288 (1996)
13		C. P. Ravikumar, R. Aggarwal: Parallel search-and-learn techniques and graph coloring. Knowl.-Based Syst. 9(1): 3-13 (1996)
	1995
12		C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal: A STAFAN-like functional testability measure for register-level circuits. Asian Test Symposium 1995: 192-198
11		C. P. Ravikumar, Hemant Joshi: HISCOAP: a hierarchical testability analysis tool. VLSI Design 1995: 272-277
10		C. P. Ravikumar, Naresh Vedi: Heuristic and neural algorithms for mapping tasks to a reconfigurable array. Microprocessing and Microprogramming 41(2): 137-151 (1995)
	1994
9		C. P. Ravikumar, H. Rasheed: Simulated Annealing for Target-Oriented Scan. VLSI Design 1994: 107-112
8		C. P. Ravikumar: Parallel search-and-learn technique for solving large scale travelling-salesperson problems. Knowl.-Based Syst. 7(3): 169-176 (1994)
	1993
7		C. P. Ravikumar, A. Kuchlous, G. Manimaran: Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network. ICPP 1993: 83-90
6		C. P. Ravikumar: A Parallel Search-and-Learn Technique for Solving Large Scale TSP. ICTAI 1993: 381-388
5		C. P. Ravikumar: Solving VLSI physical design problems on a vector machine. Computer-Aided Design 25(1): 49-57 (1993)
	1992
4		C. P. Ravikumar: Interval partition with bounded overlap. Computer-Aided Design 24(8): 405-410 (1992)
	1990
3		C. P. Ravikumar, Lalit M. Patnaik: Performance improvement of simulated annealing algorithms. Comput. Syst. Sci. Eng. 5(2): 111-115 (1990)
	1989
2		C. P. Ravikumar, Sarma Sastry: Parallel Placement on Hypercube Architecture. ICPP (3) 1989: 97-101
	1987
1		C. P. Ravikumar, Lalit M. Patnaik: An Architecture for CSP and Its Simulation. ICPP 1987: 874-881

Coauthor Index

1	Mohammed Fadle Abdulla	[15] [24] [27] [28] [30] [33] [37] [44] [59]
2	Parul Agarwal	[19] [20]
3	R. Aggarwal	[13] [25]
4	Nidhi Agrawal	[12] [14] [19] [26] [35]
5	Nitin Agrawal	[20]
6	Nisar Ahmed	[63] [69]
7	Bashir M. Al-Hashimi	[67]
8	Rajneesh Bajpai	[29]
9	Mirza Mohd. Sufyan Beg	[56]
10	Kenneth M. Butler	[69]
11	S. Chakraverty	[47] [54]
12	Gaurav Chandra	[43] [45]
13	Nitin Chandrachoodan	[79]
14	Saurabh Chopra	[57]
15	D. Roy Choudhuri	[54]
16	Vishal Dalal	[51]
17	R. Dandamudi	[64]
18	V. R. Devanathan	[64] [66] [70] [73] [75] [76]
19	Anurag Dod	[23]
20	Mohammed ElShoukry	[65] [72]
21	R. Govindarajan	[74] [77] [78]
22	Sumit Gupta	[34]
23	N. Haldar	[64]
24	Jörg Henkel	[81]
25	Dong-Hyun Heo	[22] [31]
26	Graham Hetherington	[62]
27	M. Hirech	[80]
28	Lavmeet S. Hora	[16]
29	Prachi Jain	[40]
30	Vikas Jain	[23]
31	Akshay Jajoo	[34]
32	Hemant Joshi	[11]
33	Nitin Kakkar	[57]
34	V. Kamakoti	[66] [70] [73] [75] [76]
35	Rajesh Kannah	[48]
36	Ali Keshavarzi	[81]
37	K. Kiran	[64]
38	Aman Kokrady	[58] [60] [79]
39	Hana Kubatova	[67]
40	A. Kuchlous	[7]
41	Anshul Kumar	[15] [24] [27] [28] [30] [33] [37] [44]
42	Girish Kumar	[41]
43	P. S. Vijay Kumar	[64]
44	Rahul Kumar	[52] [53]
45	T. S. Rajesh Kumar	[74] [77] [78]
46	G. Manimaran (Govindarasu Manimaran)	[7]
47	Erik Jan Marinissen	[67]
48	Ajay Mittal	[38]
49	D. Nagchoudhuri	[55]
50	S. K. Nandy (Soumitra Kumar Nandy)	[68]
51	Nishit Narang	[41]
52	Ondrej Novák	[67]
53	Jari Nurmi	[71]
54	Vojin G. Oklobdzija	[81]
55	Barry M. Pangrle	[81]
56	Alice C. Parker	[22] [31] [32]
57	Lalit M. Patnaik	[1] [3]
58	R. K. Patney	[39]
59	James F. Plusquellic (Jim Plusquellic)	[63]
60	Mukul R. Prasad	[16]
61	N. Satya Prasad	[36]
62	Tarun Rai	[21]
63	Rajamani Rajarajan	[18]
64	H. Rasheed	[9]
65	Vineet Sahula	[49] [55]
66	Sarma Sastry	[2]
67	Gurjeet S. Saund	[12]
68	V. Saxena	[17]
69	Arasu T. Senthil	[68]
70	Anil Sharma	[46]
71	C. Sharma	[25]
72	Manish Sharma	[39]
73	Meeta Sharma	[40]
74	Rohit Sharma	[42]
75	Mitra Subhasish	[67]
76	V. Sankara Subramanian	[50]
77	Mohammad Tehranipoor	[63] [65] [69] [72]
78	Naresh Vedi	[10]
79	Ashutosh Verma	[43] [45]
80	Varun Verma	[21]
81	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[81]
82	Suhrid A. Wadekar	[32]
83	X. Wen	[80]

Colors in the list of coauthors