| 2011 | ||
|---|---|---|
| 20 | Oswaldo Olivo, Sandip Ray, Jayanta Bhadra, Vivekananda M. Vedula: A Unified Formal Framework for Analyzing Functional and Speed-path Properties. MTV 2011: 44-45 | |
| 19 | Michael J. C. Gordon, Matt Kaufmann, Sandip Ray: The Right Tools for the Job: Correctness of Cone of Influence Reduction Proved Using ACL2 and HOL4. J. Autom. Reasoning 47(1): 1-16 (2011) | |
| 2010 | ||
| 18 | Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang: Optimizing equivalence checking for behavioral synthesis. DATE 2010: 1500-1505 | |
| 17 | Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronald Syzdek: Modeling and verification of industrial flash memories. ISQED 2010: 705-712 | |
| 16 | Sandip Ray, Jayanta Bhadra: Innovative practices session 7C: Verification and testing challenges in high-level synthesis. VTS 2010: 250 | |
| 2009 | ||
| 15 | Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Yang: Formal Verification for High-Assurance Behavioral Synthesis. ATVA 2009: 337-351 | |
| 14 | Sandip Ray, Warren A. Hunt Jr.: Connecting pre-silicon and post-silicon verification. FMCAD 2009: 160-163 | |
| 13 | Matt Kaufmann, J. Strother Moore, Sandip Ray, Erik Reeber: Integrating external deduction tools with ACL2. J. Applied Logic 7(1): 3-25 (2009) | |
| 2008 | ||
| 12 | Warren A. Hunt Jr., Robert Bellarmine Krug, Sandip Ray, William D. Young: Mechanized Information Flow Analysis through Inductive Assertions. FMCAD 2008: 1-4 | |
| 11 | Sandip Ray: Abstraction as a Practical Debugging Tool. MTV 2008: 45-48 | |
| 10 | Sandip Ray, Warren A. Hunt Jr., John Matthews, J. Strother Moore: A Mechanical Analysis of Program Verification Strategies. J. Autom. Reasoning 40(4): 245-269 (2008) | |
| 9 | David A. Greve, Matt Kaufmann, Panagiotis Manolios, J. Strother Moore, Sandip Ray, José-Luis Ruiz-Reina, Rob Sumners, Daron Vroon, Matthew Wilding: Efficient execution in an automated reasoning environment. J. Funct. Program. 18(1): 15-46 (2008) | |
| 2007 | ||
| 8 | Sandip Ray, Jayanta Bhadra: A Mechanized Refinement Framework for Analysis of Custom Memories. FMCAD 2007: 239-242 | |
| 7 | Sandip Ray, Warren A. Hunt Jr.: Mechanized Certification of Secure Hardware Designs. MTV 2007: 25-32 | |
| 6 | Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray: A Survey of Hybrid Techniques for Functional Verification. IEEE Design & Test of Computers 24(2): 112-122 (2007) | |
| 5 | Sandip Ray, Rob Sumners: Combining Theorem Proving with Model Checking through Predicate Abstraction. IEEE Design & Test of Computers 24(2): 132-139 (2007) | |
| 2006 | ||
| 4 | Sandip Ray: Quantification in tail-recursive function definitions. ACL2 2006: 95-98 | |
| 3 | John Matthews, J. Strother Moore, Sandip Ray, Daron Vroon: Verification Condition Generation Via Theorem Proving. LPAR 2006: 362-376 | |
| 2004 | ||
| 2 | Sandip Ray, Warren A. Hunt Jr.: Deductive Verification of Pipelined Machines Using First-Order Quantification. CAV 2004: 31-43 | |
| 1 | Sandip Ray, J. Strother Moore: Proof Styles in Operational Semantics. FMCAD 2004: 67-81 | |
| 1 | Magdy S. Abadir | [6] |
| 2 | Jayanta Bhadra (Jay Bhadra) | [6] [8] [16] [17] [20] |
| 3 | Yan Chen | [15] |
| 4 | Michael J. C. Gordon | [19] |
| 5 | David A. Greve | [9] |
| 6 | Kecheng Hao | [15] [18] |
| 7 | Warren A. Hunt Jr. | [2] [7] [10] [12] [14] |
| 8 | Matt Kaufmann | [9] [13] [19] |
| 9 | Robert Bellarmine Krug | [12] |
| 10 | Panagiotis Manolios (Pete Manolios) | [9] |
| 11 | John Matthews | [3] [10] |
| 12 | J. Strother Moore | [1] [3] [9] [10] [13] |
| 13 | Oswaldo Olivo | [20] |
| 14 | Thomas Portlock | [17] |
| 15 | Erik Reeber | [13] |
| 16 | José-Luis Ruiz-Reina | [9] |
| 17 | Robert W. Sumners (Rob Sumners) | [5] [9] |
| 18 | Ronald Syzdek | [17] |
| 19 | Vivekananda M. Vedula | [20] |
| 20 | Daron Vroon | [3] [9] |
| 21 | Li-C. Wang | [6] |
| 22 | Matthew Wilding | [9] |
| 23 | Fei Xie | [15] [18] |
| 24 | Jin Yang | [15] [18] |
| 25 | William D. Young | [12] |
Colors in the list of coauthors
Last update Sat May 26 02:31:23 2012 CET by the DBLP Team —
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