Jeff Rearick Coauthor index DBLP Vis pubzone.org

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DBLP keys2008
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLBart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick: Overview of Debug Standardization Activities. IEEE Design & Test of Computers 25(3): 258-267 (2008)
2007
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDonghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick: Empirical Validation of Yield Recovery Using Idle-Cycle Insertion. IEEE Design & Test of Computers 24(4): 362-372 (2007)
2004
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJeff Rearick, Sylvia Patterson, Krista Dorner: Integrating Boundary Scan into Multi-GHz I/O Circuitry. ITC 2004: 560-566
2003
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuzette Vandivier, Mark Wahl, Jeff Rearick: First IC Validation of IEEE Std. 1149.6. ITC 2003: 632-639
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLManish Sharma, Janak H. Patel, Jeff Rearick: Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. VTS 2003: 15-21
2001
8no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYoung Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick: Frequency detection-based boundary-scan testing of AC coupled nets. ITC 2001: 46-53
7no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJeff Rearick: Too much delay fault coverage is a bad thing. ITC 2001: 624-633
2000
6no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPeter C. Maxwell, Jeff Rearick: Deception by design: fooling ourselves with gate-level models. ITC 2000: 921-929
1999
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJeff Rearick: Practical scan test generation and application for embedded FIFOs. ITC 1999: 294-300
1998
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPeter C. Maxwell, Jeff Rearick: Estimation of defect-free IDDQ in submicron circuits using switch level simulation. ITC 1998: 882-889
1997
3no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJeff Rearick: The Case of Partial Scan. ITC 1997: 1032
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJeff Rearick: Buying time for the stuck-at fault model. ITC 1997: 1167
1993
1no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJeff Rearick, Janak H. Patel: Fast and Accurate CMOS Bridging Fault Simulation. ITC 1993: 54-62

Coauthor Index

1Krista Dorner [11]
2Young Kim [8]
3Rolf Kühnis [13]
4Benny Lai [8]
5Donghwi Lee [12]
6Peter C. Maxwell [4] [6]
7Intaik Park [12]
8Kenneth P. Parker [8]
9Janak H. Patel [1] [9]
10Sylvia Patterson [11]
11Manish Sharma [9]
12Neal Stollon [13]
13Gary Swoboda [13]
14Suzette Vandivier [10]
15Bart Vermeulen [13]
16Erik H. Volkerink [12]
17Mark Wahl [10]

Colors in the list of coauthors

Copyright © Tue Dec 1 12:01:14 2009 by Michael Ley (ley@uni-trier.de)