 | 2008 |
| 13 |  | Bart Vermeulen,
Neal Stollon,
Rolf Kühnis,
Gary Swoboda,
Jeff Rearick:
Overview of Debug Standardization Activities.
IEEE Design & Test of Computers 25(3): 258-267 (2008) |
| 2007 |
| 12 |  | Donghwi Lee,
Erik H. Volkerink,
Intaik Park,
Jeff Rearick:
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion.
IEEE Design & Test of Computers 24(4): 362-372 (2007) |
| 2004 |
| 11 |  | Jeff Rearick,
Sylvia Patterson,
Krista Dorner:
Integrating Boundary Scan into Multi-GHz I/O Circuitry.
ITC 2004: 560-566 |
| 2003 |
| 10 |  | Suzette Vandivier,
Mark Wahl,
Jeff Rearick:
First IC Validation of IEEE Std. 1149.6.
ITC 2003: 632-639 |
| 9 |  | Manish Sharma,
Janak H. Patel,
Jeff Rearick:
Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture.
VTS 2003: 15-21 |
| 2001 |
| 8 |  | Young Kim,
Benny Lai,
Kenneth P. Parker,
Jeff Rearick:
Frequency detection-based boundary-scan testing of AC coupled nets.
ITC 2001: 46-53 |
| 7 |  | Jeff Rearick:
Too much delay fault coverage is a bad thing.
ITC 2001: 624-633 |
| 2000 |
| 6 |  | Peter C. Maxwell,
Jeff Rearick:
Deception by design: fooling ourselves with gate-level models.
ITC 2000: 921-929 |
| 1999 |
| 5 |  | Jeff Rearick:
Practical scan test generation and application for embedded FIFOs.
ITC 1999: 294-300 |
| 1998 |
| 4 |  | Peter C. Maxwell,
Jeff Rearick:
Estimation of defect-free IDDQ in submicron circuits using switch level simulation.
ITC 1998: 882-889 |
| 1997 |
| 3 |  | Jeff Rearick:
The Case of Partial Scan.
ITC 1997: 1032 |
| 2 |  | Jeff Rearick:
Buying time for the stuck-at fault model.
ITC 1997: 1167 |
| 1993 |
| 1 |  | Jeff Rearick,
Janak H. Patel:
Fast and Accurate CMOS Bridging Fault Simulation.
ITC 1993: 54-62 |