 | 2009 |
|---|
| 38 |       | Michael Kadin,
Sherief Reda,
Augustus K. Uht:
Central vs. distributed dynamic thermal management for multi-core processors: which one is better?
ACM Great Lakes Symposium on VLSI 2009: 137-140 |
| 37 | | Roto Le,
Sherief Reda,
R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures.
ACM Great Lakes Symposium on VLSI 2009: 251-256 |
| 36 | | Ryan Cochran,
Sherief Reda:
Spectral techniques for high-resolution thermal characterization with limited sensor data.
DAC 2009: 478-483 |
| 35 | | Sherief Reda,
Sani R. Nassif:
Analyzing the impact of process variations on parametric measurements: Novel models and applications.
DATE 2009: 375-380 |
| 34 | | Roto Le,
Sherief Reda,
R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures.
FPGA 2009: 286 |
| 2008 |
|---|
| 33 | | Brendan Hargreaves,
Henrik Hult,
Sherief Reda:
Within-die process variations: How accurately can they be statistically modeled?
ASP-DAC 2008: 524-530 |
| 32 | | Michael Kadin,
Sherief Reda:
Frequency and voltage planning for multi-core processors under thermal constraints.
ICCD 2008: 463-470 |
| 31 | | Michael Kadin,
Sherief Reda:
Frequency planning for multi-core processors under thermal constraints.
ISLPED 2008: 213-216 |
| 30 | | Cesare Ferri,
Sherief Reda,
R. Iris Bahar:
Parametric yield management for 3D ICs: Models and strategies for improvement.
JETC 4(4): (2008) |
| 2007 |
|---|
| 29 | | Cesare Ferri,
Sherief Reda,
R. Iris Bahar:
Strategies for improving the parametric yield and profits of 3D ICs.
ICCAD 2007: 220-226 |
| 28 | | David Meisner,
Sherief Reda:
Hardware libraries: An architecture for economic acceleration in soft multi-core environments.
ICCD 2007: 179-186 |
| 27 | | Andrew B. Kahng,
Sherief Reda,
Puneet Sharma:
On-Line Adjustable Buffering for Runtime Power Reduction.
ISQED 2007: 550-555 |
| 2006 |
|---|
| 26 | | Sherief Reda,
Amit Chowdhary:
Effective linear programming based placement methods.
ISPD 2006: 186-191 |
| 25 | | Andrew B. Kahng,
Sherief Reda:
A tale of two nets: studies of wirelength progression in physical design.
SLIP 2006: 17-24 |
| 24 | | Andrew B. Kahng,
Sherief Reda:
Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2806-2819 (2006) |
| 23 | | Andrew B. Kahng,
Ion I. Mandoiu,
Sherief Reda,
Xu Xu,
Alexander Zelikovsky:
Computer-Aided Optimization of DNA Array Design and Manufacturing.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(2): 305-320 (2006) |
| 22 | | Andrew B. Kahng,
Sherief Reda:
New and improved BIST diagnosis methods from combinatorial Group testing theory.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 533-543 (2006) |
| 21 | | Gi-Joon Nam,
Sherief Reda,
Charles J. Alpert,
Paul Villarrubia,
Andrew B. Kahng:
A Fast Hierarchical Quadratic Placement Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 678-691 (2006) |
| 20 | | Andrew B. Kahng,
Sherief Reda:
Wirelength minimization for min-cut placements via placement feedback.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1301-1312 (2006) |
| 2005 |
|---|
| 19 | | Yongseok Cheon,
Pei-Hsin Ho,
Andrew B. Kahng,
Sherief Reda,
Qinke Wang:
Power-aware placement.
DAC 2005: 795-800 |
| 18 |  | Andrew B. Kahng,
Sherief Reda:
Intrinsic shortest path length: a new, accurate a priori wirelength estimator.
ICCAD 2005: 173-180 |
| 17 | | Andrew B. Kahng,
Sherief Reda,
Qinke Wang:
Architecture and details of a high quality, large-scale analytical placer.
ICCAD 2005: 891-898 |
| 16 | | Charles J. Alpert,
Andrew B. Kahng,
Gi-Joon Nam,
Sherief Reda,
Paul Villarrubia:
A semi-persistent clustering technique for VLSI circuit placement.
ISPD 2005: 200-207 |
| 15 | | Andrew B. Kahng,
Sherief Reda:
Evaluation of placer suboptimality via zero-change netlist transformations.
ISPD 2005: 208-215 |
| 14 | | Andrew B. Kahng,
Sherief Reda,
Qinke Wang:
APlace: a general analytic placement framework.
ISPD 2005: 233-235 |
| 2004 |
|---|
| 13 | | Andrew B. Kahng,
Igor L. Markov,
Sherief Reda:
On legalization of row-based placements.
ACM Great Lakes Symposium on VLSI 2004: 214-219 |
| 12 | | Andrew B. Kahng,
Sherief Reda:
Combinatorial group testing methods for the BIST diagnosis problem.
ASP-DAC 2004: 113-116 |
| 11 | | Andrew B. Kahng,
Sherief Reda:
Placement feedback: a concept and method for better min-cut placements.
DAC 2004: 357-362 |
| 10 | | Andrew B. Kahng,
Igor L. Markov,
Sherief Reda:
Boosting: Min-Cut Placement with Improved Signal Delay.
DATE 2004: 1098-1103 |
| 9 | | Andrew B. Kahng,
Ion I. Mandoiu,
Pavel A. Pevzner,
Sherief Reda,
Alexander Zelikovsky:
Scalable Heuristics for Design of DNA Probe Arrays.
Journal of Computational Biology 11(2/3): 429-447 (2004) |
| 8 | | Andrew B. Kahng,
Sherief Reda:
Match twice and stitch: a new TSP tour construction heuristic.
Oper. Res. Lett. 32(6): 499-509 (2004) |
| 2003 |
|---|
| 7 | | Andrew B. Kahng,
Ion I. Mandoiu,
Sherief Reda,
Xu Xu,
Alexander Zelikovsky:
Evaluation of Placement Techniques for DNA Probe Array Layout.
ICCAD 2003: 262-269 |
| 6 | | Andrew B. Kahng,
Ion I. Mandoiu,
Sherief Reda,
Xu Xu,
Alexander Zelikovsky:
Design Flow Enhancements for DNA Arrays.
ICCD 2003: 116- |
| 5 | | Andrew B. Kahng,
Ion I. Mandoiu,
Pavel A. Pevzner,
Sherief Reda,
Alexander Zelikovsky:
Engineering a scalable placement heuristic for DNA probe arrays.
RECOMB 2003: 148-156 |
| 2002 |
|---|
| 4 | | Sherief Reda,
Alex Orailoglu:
Reducing Test Application Time Through Test Data Mutation Encoding.
DATE 2002: 387-395 |
| 3 | | Sherief Reda,
Rolf Drechsler,
Alex Orailoglu:
On the Relation between SAT and BDDs for Equivalence Checking.
ISQED 2002: 394-399 |
| 2 | | Andrew B. Kahng,
Ion I. Mandoiu,
Pavel A. Pevzner,
Sherief Reda,
Alexander Zelikovsky:
Border Length Minimization in DNA Array Design.
WABI 2002: 435-448 |
| 2001 |
|---|
| 1 | | Sherief Reda,
A. Salem:
Combinational equivalence checking using Boolean satisfiability and binary decision diagrams.
DATE 2001: 122-126 |
