Francesco Regazzoni

	2009
11		Francesco Regazzoni, Alessandro Cevrero, François-Xavier Standaert, Stéphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne: A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. CHES 2009: 205-219
10		Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Transactions on Computational Science 4: 230-243 (2009)
	2008
9		Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, Israel Koren: Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?. DFT 2008: 202-210
8		Guido Marco Bertoni, Luca Breveglieri, Roberto Farina, Francesco Regazzoni: A 640 Mbit/S 32-Bit Pipelined Implementation of the AES Algorithm. SECRYPT 2008: 453-459
	2007
7		André C. Nácul, Francesco Regazzoni, Marcello Lajolo: Hardware scheduling support in SMP architectures. DATE 2007: 642-647
6		Francesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar: Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits. DFT 2007: 508-516
5		Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne: A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. ICSAMOS 2007: 209-214
4		Matteo Giaconia, Marco Macchetti, Francesco Regazzoni, Kai Schramm: Area and Power Efficient Synthesis of DPA-Resistant Cryptographic S-Boxes. VLSI Design 2007: 731-737
	2006
3		Sathish Chandra, Francesco Regazzoni, Marcello Lajolo: Hardware/software partitioning of operating systems: a behavioral synthesis approach. ACM Great Lakes Symposium on VLSI 2006: 324-329
2		Guido Bertoni, Luca Breveglieri, Roberto Farina, Francesco Regazzoni: Speeding Up AES By Extending a 32 bit Processor Instruction Set. ASAP 2006: 275-282
	2005
1		Francesco Regazzoni, André C. Nácul, Marcello Lajolo: Automatic synthesis of the Hardware/Software Interface. FDL 2005: 401-405

Coauthor Index

1	Stéphane Badel	[5] [11]
2	Guido Bertoni (Guido Marco Bertoni)	[2] [8]
3	Luca Breveglieri	[2] [6] [8] [9]
4	Philip Brisk	[11]
5	Alessandro Cevrero	[11]
6	Sathish Chandra	[3]
7	Zeynep Toprak Deniz	[5] [10]
8	Thomas Eisenbarth	[5] [6] [9] [10]
9	Roberto Farina	[2] [8]
10	Matteo Giaconia	[4]
11	Johann Großschädl	[5] [6] [10]
12	Frank K. Gürkaynak	[10]
13	Paolo Ienne	[5] [6] [9] [10] [11]
14	Theo Kluter	[11]
15	Israel Koren	[6] [9]
16	Marcello Lajolo	[1] [3] [7]
17	Yusuf Leblebici	[5] [10] [11]
18	Marco Macchetti	[4] [5] [10]
19	André C. Nácul	[1] [7]
20	Christof Paar	[5] [6] [10]
21	Axel Poschmann	[5] [10]
22	Laura Pozzi	[5] [10]
23	Kai Schramm	[4]
24	François-Xavier Standaert	[11]

Colors in the list of coauthors