Thara Rejimon

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2006

3 Thara Rejimon, Sanjukta Bhanja: Wide Limited Switch Dynamic Logic Circuit Implementations. VLSI Design 2006: 94-99

2 Thara Rejimon, Sanjukta Bhanja: A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis. IEEE Trans. VLSI Syst. 14(10): 1130-1139 (2006)

2005

1 Thara Rejimon, Sanjukta Bhanja: An Accurate Probalistic Model for Error Detection. VLSI Design 2005: 717-722

	2006
3		Thara Rejimon, Sanjukta Bhanja: Wide Limited Switch Dynamic Logic Circuit Implementations. VLSI Design 2006: 94-99
2		Thara Rejimon, Sanjukta Bhanja: A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis. IEEE Trans. VLSI Syst. 14(10): 1130-1139 (2006)
	2005
1		Thara Rejimon, Sanjukta Bhanja: An Accurate Probalistic Model for Error Detection. VLSI Design 2005: 717-722

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