| 2009 | ||
|---|---|---|
| 61 | Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard: A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. ISLPED 2009: 225-230 | |
| 2008 | ||
| 60 | Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin: Physical Design of FPGA Interconnect to Prevent Information Leakage. ARC 2008: 87-98 | |
| 2007 | ||
| 59 | Cedric Koch-Hofer, Marc Renaudin: Timed Asynchronous Circuits Modeling using SystemC. FDL 2007: 110-115 | |
| 58 | Yannick Monnet, Marc Renaudin, Régis Leveugle: Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS 2007: 113-120 | |
| 57 | Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet: ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC. NOCS 2007: 295-306 | |
| 56 | Sylvain Miermont, Pascal Vivet, Marc Renaudin: A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling. PATMOS 2007: 556-565 | |
| 55 | Mischa Dohler, Dominique Barthel, Florence Maraninchi, Laurent Mounier, Stephane Aubert, Christophe Dugas, Aurélien Buhrig, Franck Paugnat, Marc Renaudin, Andrzej Duda, Martin Heusse, Fabrice Valois: The ARESA Project: Facilitating Research, Development and Commercialization of WSNs. SECON 2007: 590-599 | |
| 54 | Julien Goulier, Eric André, Marc Renaudin: A new analytical approach of the impact of jitter on continuous time delta sigma converters. VLSI-SoC 2007: 110-115 | |
| 53 | G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain: DPA on quasi delay insensitive asynchronous circuits: formalization and improvement CoRR abs/0710.3443: (2007) | |
| 52 | N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic CoRR abs/0710.4711: (2007) | |
| 51 | Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon: Parallel Asynchronous Watershed Algorithm-Architecture. IEEE Trans. Parallel Distrib. Syst. 18(1): 44-56 (2007) | |
| 50 | J. Fragoso, Gilles Sicard, Marc Renaudin: Estimation rapide du couple énergie/délai des circuits asynchrones QDI. Technique et Science Informatiques 26(5): 535-565 (2007) | |
| 2006 | ||
| 49 | D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin: AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation. ASYNC 2006: 86-97 | |
| 48 | G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. CHES 2006: 384-398 | |
| 47 | Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel: Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC 2006: 88-97 | |
| 46 | Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet: Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS 2006: 125-130 | |
| 45 | Marc Renaudin, Yannick Monnet: Asynchronous Design: Fault Robustness and Security Characteristics. IOLTS 2006: 92-95 | |
| 44 | Eslam Yahya, Marc Renaudin: QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis. PATMOS 2006: 583-592 | |
| 43 | Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin: State-holding in Look-Up Tables: application to asynchronous logic. VLSI-SoC 2006: 12-17 | |
| 42 | Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin: Security evaluation of dual rail logic against DPA attacks. VLSI-SoC 2006: 181-186 | |
| 41 | Yannick Monnet, Marc Renaudin, Régis Leveugle: Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers 55(9): 1104-1115 (2006) | |
| 40 | David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin: On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits. J. Low Power Electronics 2(1): 45-55 (2006) | |
| 2005 | ||
| 39 | Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin: An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework. ASYNC 2005: 54-63 | |
| 38 | Yannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous circuits transient faults sensitivity evaluation. DAC 2005: 863-868 | |
| 37 | N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin: FPGA Architecture for Multi-Style Asynchronous Logic. DATE 2005: 32-33 | |
| 36 | G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain: DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. DATE 2005: 424-429 | |
| 35 | Laurent Fesquet, Marc Renaudin: A Programmable Logic Architecture for Prototyping Clockless Circuits. FPL 2005: 293-298 | |
| 34 | Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin: GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. FPL 2005: 299-304 | |
| 33 | Yannick Monnet, Marc Renaudin, Régis Leveugle: Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS 2005: 129-134 | |
| 32 | Emmanuel Allier, Julien Goulier, Gilles Sicard, A. Dezzani, Eric André, Marc Renaudin: A 120nm low power asynchronous ADC. ISLPED 2005: 60-65 | |
| 31 | David Rios-Arambula, Aurélien Buhrig, Marc Renaudin: Power Consumption Reduction Using Dynamic Control of Micro Processor Performance. PATMOS 2005: 10-18 | |
| 30 | Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine: A Method to Design Compact Dual-rail Asynchronous Primitives. PATMOS 2005: 571-580 | |
| 29 | Laurent Fesquet, Jerome Quartana, Marc Renaudin: Asynchronous Systems on Programmable Logic. ReCoSoC 2005: 105-112 | |
| 28 | G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard: Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. VLSI-SoC 2005: 11-24 | |
| 27 | Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. VLSI-SoC 2005: 195-207 | |
| 26 | Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin: Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. VLSI-SoC 2005: 55-69 | |
| 2004 | ||
| 25 | F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin: Asynchronous FIR Filters: Towards a New Digital Processing Chain. ASYNC 2004: 198-206 | |
| 24 | Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain: High Security Smartcards. DATE 2004: 228-233 | |
| 23 | Yannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous Circuits Sensitivity to Fault Injection. IOLTS 2004: 121-128 | |
| 22 | Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin: TAST Profiler and Low Energy Asynchronous Design Methodology. PATMOS 2004: 268-277 | |
| 21 | Dhanistha Panyasak, Gilles Sicard, Marc Renaudin: A current shaping methodology for lowering em disturbances in asynchronous circuits. Microelectronics Journal 35(6): 531-540 (2004) | |
| 2003 | ||
| 20 | Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin: A New Class of Asynchronous A/D Converters Based on Time Quantization. ASYNC 2003: 196-205 | |
| 19 | Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni: An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. HICSS 2003: 279 | |
| 18 | João Leonardo Fragoso, Gilles Sicard, Marc Renaudin: Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders. PATMOS 2003: 171-180 | |
| 17 | Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin: Statistic Implementation of QDI Asynchronous Primitives. PATMOS 2003: 181-191 | |
| 16 | João Leonardo Fragoso, Gilles Sicard, Marc Renaudin: Automatic Generation of 1-of-M QDI Asynchronous Adders. SBCCI 2003: 149-154 | |
| 15 | Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni: Validation of asynchronous circuit specifications using IF/CADP. VLSI-SOC 2003: 86-91 | |
| 2002 | ||
| 14 | Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana: High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. DATE 2002: 1090 | |
| 13 | Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland: Implementing Asynchronous Circuits on LUT Based FPGAs. FPL 2002: 36-46 | |
| 12 | Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin: Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196 | |
| 11 | Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin: Dynamic Voltage Scheduling for Real Time Asynchronous Systems. PATMOS 2002: 390-399 | |
| 10 | Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard: Low-Power Asynchronous A/D Conversion. PATMOS 2002: 81-91 | |
| 2001 | ||
| 9 | Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés: Low-power systems on chips (SOCs). DATE 2001: 488 | |
| 8 | Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin: Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. VLSI-SOC 2001: 313-324 | |
| 1999 | ||
| 7 | Marc Renaudin, Pascal Vivet, Frédéric Robin: A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation. ASYNC 1999: 135-144 | |
| 1998 | ||
| 6 | Marc Renaudin, Pascal Vivet, Frédéric Robin: ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. ASYNC 1998: 22-31 | |
| 1997 | ||
| 5 | Frédéric Robin, Gilles Privat, Marc Renaudin: Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective. IJPRAI 11(7): 1085-1094 (1997) | |
| 1996 | ||
| 4 | Alain Guyot, Marc Renaudin, Bachar El Hassan, Volker Levering: Self timed division and square-root extraction. VLSI Design 1996: 376-381 | |
| 1995 | ||
| 3 | Gilles Privat, Frédéric Robin, Marc Renaudin, Bachar El Hassan: A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture. ISCAS 1995: 1041-1044 | |
| 1994 | ||
| 2 | Marc Renaudin, Bachar El Hassan: The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic. ISCAS 1994: 291-294 | |
| 1993 | ||
| 1 | A. K. Betts, Ivo Bolsens, E. Sicard, Marc Renaudin, A. Johnstone: SMILE: A scalable microcontroller library element. Microprocessing and Microprogramming 39(2-5): 259-262 (1993) | |