 | 2009 |
|---|
| 204 |       | Matteo Sonza Reorda,
Massimo Violante,
Cristina Meinhardt,
Ricardo Reis:
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips.
DATE 2009: 352-357 |
| 203 | | L. Ciganda,
Francesco Abate,
Paolo Bernardi,
M. Bruno,
Matteo Sonza Reorda:
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.
DDECS 2009: 258-263 |
| 202 | | Alberto Bosio,
Patrick Girard,
Serge Pravossoudovitch,
Paolo Bernardi,
Matteo Sonza Reorda:
An efficient fault simulation technique for transition faults in non-scan sequential circuits.
DDECS 2009: 50-55 |
| 201 | | Andreas Apostolakis,
Dimitris Gizopoulos,
Mihalis Psarakis,
Danilo Ravotto,
Matteo Sonza Reorda:
Test Program Generation for Communication Peripherals in Processor-Based SoC Devices.
IEEE Design & Test of Computers 26(2): 52-63 (2009) |
| 2008 |
|---|
| 200 | | Paolo Bernardi,
Matteo Sonza Reorda:
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers.
DATE 2008: 194-199 |
| 199 | | Wilson J. Perez,
Jaime Velasco-Medina,
Danilo Ravotto,
Edgar E. Sánchez,
Matteo Sonza Reorda:
Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs.
DDECS 2008: 339-344 |
| 198 | | Paolo Bernardi,
Kyriakos Christou,
Michelangelo Grosso,
Maria K. Michael,
Ernesto Sánchez,
Matteo Sonza Reorda:
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.
EvoWorkshops 2008: 224-234 |
| 197 | | Kyriakos Christou,
Maria K. Michael,
Paolo Bernardi,
Michelangelo Grosso,
Ernesto Sánchez,
Matteo Sonza Reorda:
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.
VTS 2008: 389-394 |
| 196 | | Paolo Bernardi,
Ernesto Sánchez,
Massimiliano Schillaci,
Giovanni Squillero,
Matteo Sonza Reorda:
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 570-574 (2008) |
| 195 | | Eduardo Luis Rhod,
Carlos Arthur Lang Lisbôa,
Luigi Carro,
Matteo Sonza Reorda,
Massimo Violante:
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.
J. Electronic Testing 24(1-3): 45-56 (2008) |
| 2007 |
|---|
| 194 | | Paolo Bernardi,
Michelangelo Grosso,
Matteo Sonza Reorda:
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems.
ACM Great Lakes Symposium on VLSI 2007: 411-416 |
| 193 | | Ernesto Sánchez,
Massimiliano Schillaci,
Giovanni Squillero,
Matteo Sonza Reorda:
Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor.
DATE 2007: 1158-1163 |
| 192 |  | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Matteo Sonza Reorda:
Extended Fault Detection Techniques for Systems-on-Chip.
DDECS 2007: 55-60 |
| 191 | | Jorge Luis Lagos-Benites,
Davide Appello,
Paolo Bernardi,
Michelangelo Grosso,
Danilo Ravotto,
Edgar E. Sánchez,
Matteo Sonza Reorda:
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.
DFT 2007: 291-300 |
| 190 | | Michelangelo Grosso,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Safety Evaluation of NanoFabrics.
DFT 2007: 418-426 |
| 189 | | Salvatore Pontarelli,
Luca Sterpone,
Gian-Carlo Cardarilli,
Marco Re,
Matteo Sonza Reorda,
Adelio Salsano,
Massimo Violante:
Optimization of Self Checking FIR filters by means of Fault Injection Analysis.
DFT 2007: 96-104 |
| 188 | | Paolo Bernardi,
Michelangelo Grosso,
Ernesto Sánchez,
Matteo Sonza Reorda:
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores.
European Test Symposium 2007: 179-184 |
| 187 | | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Matteo Sonza Reorda:
A Hybrid Approach to Fault Detection and Correction in SoCs.
IOLTS 2007: 107-112 |
| 186 | | Salvatore Pontarelli,
Luca Sterpone,
Gian-Carlo Cardarilli,
Marco Re,
Matteo Sonza Reorda,
Adelio Salsano,
Massimo Violante:
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.
IOLTS 2007: 194-196 |
| 185 | | Leticia Maria Veiras Bolzani,
Ernesto Sánchez,
Massimiliano Schillaci,
Matteo Sonza Reorda,
Giovanni Squillero:
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores.
IOLTS 2007: 265-270 |
| 184 | | Danilo Ravotto,
E. Sanchez,
Massimiliano Schillaci,
Matteo Sonza Reorda,
Giovanni Squillero:
On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.
MTV 2007: 71-76 |
| 183 | | W. Di Palma,
Danilo Ravotto,
E. Sanchez,
Massimiliano Schillaci,
Matteo Sonza Reorda,
Giovanni Squillero:
Automotive Microcontroller End-of-Line Test via Software-Based Methodologies.
MTV 2007: 77-82 |
| 182 | | Leticia Maria Veiras Bolzani,
Paolo Bernardi,
Matteo Sonza Reorda:
An optimized hybrid approach to provide fault detection and correction in SoCs.
SBCCI 2007: 342-347 |
| 181 | | Leticia Maria Veiras Bolzani,
Edgar E. Sánchez,
Matteo Sonza Reorda:
A software-based methodology for the generation of peripheral test sets based on high-level descriptions.
SBCCI 2007: 348-353 |
| 180 | | Fernanda Lima Kastensmidt,
Luca Sterpone,
Luigi Carro,
Matteo Sonza Reorda:
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
CoRR abs/0710.4688: (2007) |
| 179 | | Paolo Bernardi,
Guido Masera,
Federico Quaglio,
Matteo Sonza Reorda:
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
CoRR abs/0710.4840: (2007) |
| 178 | | Luca Sterpone,
Matteo Sonza Reorda,
Massimo Violante,
Fernanda Lima Kastensmidt,
Luigi Carro:
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.
J. Electronic Testing 23(1): 47-54 (2007) |
| 177 | | Paolo Bernardi,
Michelangelo Grosso,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A System-layer Infrastructure for SoC Diagnosis.
J. Electronic Testing 23(5): 389-404 (2007) |
| 2006 |
|---|
| 176 | | Matteo Sonza Reorda,
Ondrej Novák,
Bernd Straube,
Hana Kubatova,
Zdenek Kotásek,
Pavel Kubalík,
Raimund Ubar,
Jiri Bucek:
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006
IEEE Computer Society 2006 |
| 175 | | Paolo Bernardi,
Ernesto Sánchez,
Massimiliano Schillaci,
Giovanni Squillero,
Matteo Sonza Reorda:
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs.
DATE 2006: 412-417 |
| 174 | | Carlos Arthur Lang Lisbôa,
Luigi Carro,
Matteo Sonza Reorda,
Massimo Violante:
Online hardening of programs against SEUs and SETs.
DFT 2006: 280-290 |
| 173 | | Matteo Sonza Reorda,
Luca Sterpone,
Massimo Violante,
Marta Portela-García,
Celia López-Ongil,
Luis Entrena:
Fault Injection-based Reliability Evaluation of SoPCs.
European Test Symposium 2006: 75-82 |
| 172 | | Matteo Sonza Reorda,
Massimo Violante:
Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems.
IOLTS 2006: 229-234 |
| 171 | | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Alberto Manzone,
Marcella Guagliumi Massimo Osella,
Massimo Violante,
Matteo Sonza Reorda:
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications.
MTV 2006: 3-8 |
| 170 | | Davide Appello,
Vincenzo Tancorre,
Paolo Bernardi,
Michelangelo Grosso,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
On the Automation of the Test Flow of Complex SoCs.
VTS 2006: 166-171 |
| 169 | | Paolo Bernardi,
Michelangelo Grosso,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries.
VTS 2006: 386-391 |
| 168 | | Julio Pérez Acle,
Matteo Sonza Reorda,
Massimo Violante:
Early, Accurate Dependability Analysis of CAN-Based Networked Systems.
IEEE Design & Test of Computers 23(1): 38-45 (2006) |
| 167 | | Davide Appello,
Paolo Bernardi,
Michelangelo Grosso,
Matteo Sonza Reorda:
System-in-Package Testing: Problems and Solutions.
IEEE Design & Test of Computers 23(3): 203-211 (2006) |
| 166 | | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Fabian Vargas,
Massimo Violante:
A New Hybrid Fault Detection Technique for Systems-on-a-Chip.
IEEE Trans. Computers 55(2): 185-198 (2006) |
| 165 | | Ernesto Sánchez,
Matteo Sonza Reorda,
Giovanni Squillero:
Efficient Techniques for Automatic Verification-Oriented Test Set Optimization.
International Journal of Parallel Programming 34(1): 93-109 (2006) |
| 2005 |
|---|
| 164 | | Fernanda Lima Kastensmidt,
Luca Sterpone,
Luigi Carro,
Matteo Sonza Reorda:
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs.
DATE 2005: 1290-1295 |
| 163 | | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.
DFT 2005: 445-453 |
| 162 | | Ernesto Sánchez,
Matteo Sonza Reorda,
Giovanni Squillero:
On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors.
DFT 2005: 494-504 |
| 161 | | Paolo Bernardi,
Leticia Maria Veiras Bolzani,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Fabian Vargas,
Massimo Violante:
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.
DSN 2005: 50-58 |
| 160 | | Ernesto Sánchez,
Matteo Sonza Reorda,
Giovanni Squillero:
Automatic Completion and Refinement of Verification Sets for Microprocessor Cores.
EvoWorkshops 2005: 205-214 |
| 159 | | Ernesto Sánchez,
Massimiliano Schillaci,
Matteo Sonza Reorda,
Giovanni Squillero,
Luca Sterpone,
Massimo Violante:
New evolutionary techniques for test-program generation for complex microprocessor cores.
GECCO 2005: 2193-2194 |
| 158 | | Alberto Manzone,
Paolo Bernardi,
Michelangelo Grosso,
Maurizio Rebaudengo,
Ernesto Sánchez,
Matteo Sonza Reorda:
Integrating BIST Techniques for On-Line SoC Testing.
IOLTS 2005: 235-240 |
| 157 | | Matteo Sonza Reorda,
Luca Sterpone,
Massimo Violante:
Efficient Estimation of SEU Effects in SRAM-Based FPGAs.
IOLTS 2005: 54-59 |
| 156 | | Paolo Bernardi,
Ernesto Sánchez,
Massimiliano Schillaci,
Matteo Sonza Reorda,
Giovanni Squillero:
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets.
MTV 2005: 37-41 |
| 155 | | Paolo Bernardi,
Michelangelo Grosso,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.
MTV 2005: 55-62 |
| 154 | | Ernesto Sánchez,
Matteo Sonza Reorda,
Giovanni Squillero,
Massimo Violante:
Automatic generation of test sets for SBST of microprocessor IP cores.
SBCCI 2005: 74-79 |
| 2004 |
|---|
| 153 | | O. Goloubeva,
Matteo Sonza Reorda,
Massimo Violante:
Automatic Generation of Validation Stimuli for Application-Specific Processors.
DATE 2004: 188-193 |
| 152 | | Paolo Bernardi,
Guido Masera,
Federico Quaglio,
Matteo Sonza Reorda:
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study.
DATE 2004: 228-233 |
| 151 | | Paolo Bernardi,
Guido Masera,
Federico Quaglio,
Matteo Sonza Reorda:
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study.
DATE 2004: 228-233 |
| 150 | | M. Bellato,
Paolo Bernardi,
D. Bortolato,
A. Candelori,
M. Ceschia,
Alessandro Paccagnella,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante,
P. Zambolin:
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA.
DATE 2004: 584-589 |
| 149 | | Lorena Anghel,
Ernesto Sánchez,
Matteo Sonza Reorda,
Giovanni Squillero,
Raoul Velazco:
Coupling Different Methodologies to Validate Obsolete Microprocessors.
DFT 2004: 250-255 |
| 148 | | Paolo Bernardi,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Exploiting an I-IP for In-Field SOC Test.
DFT 2004: 404-412 |
| 147 | | Matteo Sonza Reorda,
Massimo Violante:
On-Line Analysis and Perturbation of CAN Networks.
DFT 2004: 424-432 |
| 146 | | Paolo Bernardi,
Matteo Sonza Reorda,
Luca Sterpone,
Massimo Violante:
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.
IOLTS 2004: 115-120 |
| 145 | | Leticia Maria Veiras Bolzani,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Fabian Vargas,
Massimo Violante:
Hybrid Soft Error Detection by Means of Infrastructure IP Cores.
IOLTS 2004: 79-88 |
| 144 | | Fulvio Corno,
Matteo Sonza Reorda,
S. Tosato,
F. Esposito:
Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems.
ITC 2004: 1332-1339 |
| 143 | | Paolo Bernardi,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores.
MTV 2004: 22-27 |
| 142 | | W. Lindsay,
Ernesto Sánchez,
Matteo Sonza Reorda,
Giovanni Squillero:
Automatic Test Programs Generation Driven by Internal Performance Counters.
MTV 2004: 8-13 |
| 141 | | Fulvio Corno,
Julio Pérez Acle,
Matteo Sonza Reorda,
Massimo Violante:
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol.
SBCCI 2004: 71-75 |
| 140 | | Fulvio Corno,
Ernesto Sánchez,
Matteo Sonza Reorda,
Giovanni Squillero:
Automatic Test Program Generation: A Case Study.
IEEE Design & Test of Computers 21(2): 102-109 (2004) |
| 139 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Evolutionary Simulation-Based Validation.
International Journal on Artificial Intelligence Tools 13(4): 897-916 (2004) |
| 138 | | Davide Appello,
Alessandra Fudoli,
Vincenzo Tancorre,
Paolo Bernardi,
Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
J. Electronic Testing 20(1): 79-87 (2004) |
| 137 | | Fulvio Corno,
Ernesto Sánchez,
Matteo Sonza Reorda,
Giovanni Squillero:
Code Generation for Functional Validation of Pipelined Microprocessors.
J. Electronic Testing 20(3): 269-278 (2004) |
| 136 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
A New Approach to Software-Implemented Fault Tolerance.
J. Electronic Testing 20(4): 433-437 (2004) |
| 135 | | Cecilia Metra,
Matteo Sonza Reorda:
Guest Editorial.
J. Electronic Testing 20(5): 463 (2004) |
| 134 | | Matteo Sonza Reorda,
Massimo Violante:
A New Approach to the Analysis of Single Event Transients in VLSI Circuits.
J. Electronic Testing 20(5): 511-521 (2004) |
| 133 | | Matteo Sonza Reorda,
Massimo Violante:
Efficient analysis of single event transients.
Journal of Systems Architecture 50(5): 239-246 (2004) |
| 2003 |
|---|
| 132 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor.
DATE 2003: 10602-10607 |
| 131 | | Paolo Bernardi,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories.
DATE 2003: 10720-10725 |
| 130 | | Fulvio Corno,
Gianluca Cumani,
Matteo Sonza Reorda,
Giovanni Squillero:
Fully Automatic Test Program Generation for Microprocessor Cores.
DATE 2003: 11006-11011 |
| 129 | | Abdelaziz Ammari,
Régis Leveugle,
Matteo Sonza Reorda,
Massimo Violante:
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels.
DFT 2003: 336-343 |
| 128 | | J. Pérez,
Matteo Sonza Reorda,
Massimo Violante:
Dependability Analysis of CAN Networks: An Emulation-Based Approach.
DFT 2003: 537- |
| 127 | | O. Goloubeva,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Soft-Error Detection Using Control Flow Assertions.
DFT 2003: 581-588 |
| 126 | | Matteo Sonza Reorda,
Massimo Violante:
Emulation-Based Analysis of Soft Errors in Deep Sub-micron Circuits.
FPL 2003: 616-626 |
| 125 | | Matteo Sonza Reorda,
Massimo Violante:
Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits.
IOLTS 2003: 101-105 |
| 124 | | Massimo Violante,
M. Ceschia,
Matteo Sonza Reorda,
Alessandro Paccagnella,
Paolo Bernardi,
Maurizio Rebaudengo,
D. Bortolato,
M. Bellato,
P. Zambolin,
A. Candelori:
Analyzing SEU Effects in SRAM-based FPGAs.
IOLTS 2003: 119-123 |
| 123 | | O. Goloubeva,
Matteo Sonza Reorda,
Massimo Violante:
An RT-level Concurrent Error Detection Technique for Data Dominated Systems.
IOLTS 2003: 159 |
| 122 | | Fabian Vargas,
Diogo B. Brum,
Dárcio Prestes,
Leticia Maria Veiras Bolzani,
Eduardo Luis Rhod,
Matteo Sonza Reorda:
Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy?
IOLTS 2003: 163 |
| 121 | | Davide Appello,
Paolo Bernardi,
Alessandra Fudoli,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Vincenzo Tancorre,
Massimo Violante:
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores.
ITC 2003: 379-385 |
| 120 | | Fulvio Corno,
Gianluca Cumani,
Matteo Sonza Reorda,
Giovanni Squillero:
Automatic Test Program Generation for Pipeline Processors.
SAC 2003: 736-740 |
| 119 | | J. Pérez,
Matteo Sonza Reorda,
Massimo Violante:
Accurate Dependability Analysis of CAN-Based Networked Systems.
SBCCI 2003: 337-342 |
| 118 | | Cecilia Metra,
Matteo Sonza Reorda:
Guest Editorial.
J. Electronic Testing 19(5): 499 (2003) |
| 117 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor.
J. Electronic Testing 19(5): 577-584 (2003) |
| 116 | | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
New techniques for efficiently assessing reliability of SOCs.
Microelectronics Journal 34(1): 53-61 (2003) |
| 2002 |
|---|
| 115 | | Fulvio Corno,
Gianluca Cumani,
Matteo Sonza Reorda,
Giovanni Squillero:
Evolutionary Test Program Induction for Microprocessor Design Verification.
Asian Test Symposium 2002: 368-373 |
| 114 | | Luis Berrojo,
Isabel González,
Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero,
Luis Entrena,
Celia López:
New Techniques for Speeding-Up Fault-Injection Campaigns.
DATE 2002: 847-853 |
| 113 | | Matteo Sonza Reorda,
Massimo Violante:
Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments.
DFT 2002: 263-274 |
| 112 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
A New Functional Fault Model for FPGA Application-Oriented Testing.
DFT 2002: 372-380 |
| 111 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Evolutionary Techniques for Minimizing Test Signals Application Time.
EvoWorkshops 2002: 183-189 |
| 110 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs.
FPL 2002: 607-615 |
| 109 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Analysis of SEU Effects in a Pipelined Processor.
IOLTW 2002: 112-116 |
| 108 | | Luis Berrojo,
Isabel González,
Luis Entrena,
Celia López,
Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level.
IOLTW 2002: 193 |
| 107 | | Davide Appello,
Alessandra Fudoli,
Vincenzo Tancorre,
Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
IOLTW 2002: 206-210 |
| 106 | | Fulvio Corno,
Gianluca Cumani,
Matteo Sonza Reorda,
Giovanni Squillero:
Automatic Test Program Generation from RT-Level Microprocessor Descriptions.
ISQED 2002: 120- |
| 105 | | Davide Appello,
Alessandra Fudoli,
Vincenzo Tancorre,
Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
MTDT 2002: 12-16 |
| 104 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
An evolutionary algorithm for reducing integrated-circuit test application time.
SAC 2002: 608-612 |
| 103 | | Luis Berrojo,
Isabel González,
Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero,
Luis Entrena,
Celia López:
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation.
VTS 2002: 229-236 |
| 102 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Giovanni Squillero:
Initializability analysis of synchronous sequential circuits.
ACM Trans. Design Autom. Electr. Syst. 7(2): 249-264 (2002) |
| 101 | | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits.
J. Electronic Testing 18(3): 261-271 (2002) |
| 2001 |
|---|
| 100 | | Fulvio Corno,
Gianluca Cumani,
Matteo Sonza Reorda,
Giovanni Squillero:
Effective Techniques for High-Level ATPG.
Asian Test Symposium 2001: 225- |
| 99 | | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
FPGA-Based Fault Injection for Microprocessor Systems.
Asian Test Symposium 2001: 304- |
| 98 | | Davide Appello,
Fulvio Corno,
M. Giovinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis.
Asian Test Symposium 2001: 97-102 |
| 97 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero,
Massimo Violante:
On the test of microprocessor IP cores.
DATE 2001: 209-213 |
| 96 | | Ph. Cheynet,
B. Nicolescu,
Raoul Velazco,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
System safety through automatic high-level code transformations: an experimental evaluation.
DATE 2001: 297-301 |
| 95 | | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits .
DFT 2001: 250-258 |
| 94 | | Fulvio Corno,
Gianluca Cumani,
Matteo Sonza Reorda,
Giovanni Squillero:
ARPIA: A High-Level Evolutionary Test Signal Generator.
EvoWorkshops 2001: 298-306 |
| 93 | | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits.
FPL 2001: 493-502 |
| 92 | | B. Nicolescu,
Raoul Velazco,
Matteo Sonza Reorda:
Effectiveness and Limitations of Various Software Techniques for "Soft Error" Detection: A Comparative Study.
IOLTW 2001: 172-177 |
| 91 | | Pierluigi Civera,
Luca Macchiarulo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting FPGA for Accelerating Fault Injection Experiments.
IOLTW 2001: 9-13 |
| 90 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Evolving effective CA/CSTP: BIST architectures for sequential circuits.
SAC 2001: 345-350 |
| 89 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante,
Marco Torchiano:
A Source-to-Source Compiler for Generating Dependable Software.
SCAM 2001: 35-44 |
| 88 | | Marcello Lajolo,
Matteo Sonza Reorda,
Massimo Violante:
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs.
VLSI Design 2001: 371- |
| 2000 |
|---|
| 87 | | Marcello Lajolo,
Luciano Lavagno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Automatic test bench generation for simulation-based validation.
CODES 2000: 136-140 |
| 86 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero,
Alberto Manzone,
Alessandro Pincetti:
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience.
DATE 2000: 385-389 |
| 85 | | Marcello Lajolo,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante,
Luciano Lavagno:
Evaluating System Dependability in a Co-Design Framework.
DATE 2000: 586-590 |
| 84 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Marco Torchiano,
Massimo Violante:
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications.
DFT 2000: 257-265 |
| 83 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Automatic Validation of Protocol Interfaces Described in VHDL.
EvoWorkshops 2000: 205-213 |
| 82 | | Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Prediction of Power Requirements for High-Speed Circuits.
EvoWorkshops 2000: 247-254 |
| 81 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Evolving Cellular Automata for Self-Testing Hardware.
ICES 2000: 31-40 |
| 80 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero,
Massimo Violante:
A genetic algorithm-based system for generating test programs for microprocessor IP cores.
ICTAI 2000: 195-198 |
| 79 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata.
IJCNN (6) 2000: 577-584 |
| 78 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante,
Ph. Cheynet,
B. Nicolescu,
Raoul Velazco:
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures.
IOLTW 2000: 17- |
| 77 | | B. Parrotta,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
New Techniques for Accelerating Fault Injection in VHDL Descriptions.
IOLTW 2000: 61-66 |
| 76 | | Marcello Lajolo,
Luciano Lavagno,
Matteo Sonza Reorda,
Massimo Violante:
Early Power Estimation for System-on-Chip Designs.
PATMOS 2000: 108-117 |
| 75 | | B. Parrotta,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Speeding-Up Fault Injection Campaigns in VHDL Models.
SAFECOMP 2000: 27-36 |
| 74 | | Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Giovanni Squillero,
Massimo Violante:
Low Power BIST via Non-Linear Hybrid Cellular Automata.
VTS 2000: 29-34 |
| 73 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
High-Level Observability for Effective High-Level ATPG.
VTS 2000: 411-416 |
| 72 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
RT-Level ITC'99 Benchmarks and First ATPG Results.
IEEE Design & Test of Computers 17(3): 44-53 (2000) |
| 1999 |
|---|
| 71 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms.
DATE 1999: 754-755 |
| 70 | | Maurizio Rebaudengo,
Matteo Sonza Reorda,
Marco Torchiano,
Massimo Violante:
Soft-Error Detection through Software Fault-Tolerance Techniques.
DFT 1999: 210-218 |
| 69 | | Fulvio Corno,
Matteo Sonza Reorda,
Maurizio Rebaudengo,
Massimo Violante:
Optimal Vector Selection for Low Power BIST.
DFT 1999: 219-226 |
| 68 | | Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Test Pattern Generation Under Low Power Constraints.
EvoWorkshops 1999: 162-170 |
| 67 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms.
EvoWorkshops 1999: 182-192 |
| 66 | | Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
ALPS: A Peak Power Estimation Tool for Sequential Circuits.
Great Lakes Symposium on VLSI 1999: 350-353 |
| 65 | | Matteo Sonza Reorda:
High-level ATPG: a real topic or an academic amusement?
ITC 1999: 1118 |
| 64 | | Alfredo Benso,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems.
SAFECOMP 1999: 323-335 |
| 63 | | Maurizio Rebaudengo,
Matteo Sonza Reorda:
Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM .
VTS 1999: 452-459 |
| 62 | | Fulvio Corno,
Uwe Gläser,
Paolo Prinetto,
Matteo Sonza Reorda,
Heinrich Theodor Vierhaus,
Massimo Violante:
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 191-202 (1999) |
| 61 | | Alfredo Benso,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Fault Injection for Embedded Microprocessor-based Systems.
J. UCS 5(10): 693-711 (1999) |
| 1998 |
|---|
| 60 | | Elizabeth M. Rudnick,
Roberto Vietti,
Akilah Ellis,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques.
DATE 1998: 570-576 |
| 59 | | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection.
DATE 1998: 670- |
| 58 | | Alfredo Benso,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Pierluigi Civera:
An Integrated HW and SW Fault Injection Environment for Real-Time Systems.
DFT 1998: 117- |
| 57 | | Silvia Chiusano,
Fulvio Corno,
Matteo Sonza Reorda,
Roberto Vietti:
A System for Evaluating On-Line Testability at the RT-level.
DFT 1998: 284-291 |
| 56 | | Alfredo Benso,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A fault injection environment for microprocessor-based boards.
ITC 1998: 768-773 |
| 55 | | Fulvio Corno,
Matteo Sonza Reorda,
Giovanni Squillero:
The selfish gene algorithm: a new evolutionary optimization strategy.
SAC 1998: 349-355 |
| 54 | | Fulvio Corno,
Nicola Gaudenzi,
Paolo Prinetto,
Matteo Sonza Reorda:
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits.
VTS 1998: 424-429 |
| 53 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A Test Pattern Generation Methodology for Low-Power Consumption.
VTS 1998: 453-459 |
| 52 | | Alfredo Benso,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
EXFI: a low-cost fault injection system for embedded microprocessor-based boards.
ACM Trans. Design Autom. Electr. Syst. 3(4): 626-634 (1998) |
| 51 | | Gianpiero Cabodi,
Paolo Camurati,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
The General Product Machine: a New Model for Symbolic FSM Traversal.
Formal Methods in System Design 12(3): 267-289 (1998) |
| 50 | | Stefano Barbagallo,
Davide Medina,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Integrating Online and Offline Testing of a Switching Memory.
IEEE Design & Test of Computers 15(1): 63-70 (1998) |
| 1997 |
|---|
| 49 | | Silvia Chiusano,
Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Guaranteeing Testability in Re-encoding for Low Power.
Asian Test Symposium 1997: 30-35 |
| 48 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Giovanni Squillero:
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.
Asian Test Symposium 1997: 56-61 |
| 47 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Massimo Violante:
Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG.
Asian Test Symposium 1997: 68-73 |
| 46 | | Mario Baldi,
Fulvio Corno,
Maurizio Rebaudengo,
Paolo Prinetto,
Matteo Sonza Reorda,
Giovanni Squillero:
Simulation-based verification of network protocols performance.
CHARME 1997: 236-251 |
| 45 | | Alfredo Benso,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Jaan Raik,
Raimund Ubar:
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments.
DFT 1997: 212-217 |
| 44 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
New static compaction techniques of test sequences for sequential circuits.
ED&TC 1997: 37-43 |
| 43 | | Silvia Chiusano,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Hybrid symbolic-explicit techniques for the graph coloring problem.
ED&TC 1997: 422-426 |
| 42 | | Alfredo Benso,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Raimund Ubar:
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs.
ED&TC 1997: 560-565 |
| 41 | | F. Bianchi,
Fulvio Corno,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Roberto Ansaloni:
Boolean Function Manipulation on a Parallel System Using BDDs.
HPCN Europe 1997: 916-928 |
| 40 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Giovanni Squillero:
A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits.
ICCD 1997: 381-386 |
| 39 | | S. Chuisano,
Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization.
ICTAI 1997: 133- |
| 38 | | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Testability Analysis and ATPG on Behavioral RT-Level VHDL.
ITC 1997: 753-759 |
| 37 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits.
SAC 1997: 228-232 |
| 36 | | Silvia Chiusano,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Cellular automata for deterministic sequential test pattern generation.
VTS 1997: 60-67 |
| 1996 |
|---|
| 35 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Maurizio Damiani,
Leonardo Impagliazzo,
G. Sartore:
On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications.
EDCC 1996: 190-202 |
| 34 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits.
HPCN Europe 1996: 454-459 |
| 33 | | Gavril Godza,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Using Parallel Genetic Algorithms for Solving the Min-Cut Problem.
HPCN Europe 1996: 985-986 |
| 32 | | Maurizio Rebaudengo,
Matteo Sonza Reorda:
A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture.
HPCN Europe 1996: 987-988 |
| 31 | | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
A Genetic Algorithm for Automatic Generation of Test Logic for Digital Circuits.
ICTAI 1996: 10-16 |
| 30 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach.
ITC 1996: 39-47 |
| 29 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs.
ITC 1996: 558-564 |
| 28 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits.
PPSN 1996: 792-800 |
| 27 | | Stefano Barbagallo,
Monica Lobetti Bodoni,
Davide Medina,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Scan insertion criteria for low design impact.
VTS 1996: 26-31 |
| 26 | | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Circular Self-Test Path for FSMs.
IEEE Design & Test of Computers 13(4): 50-60 (1996) |
| 25 | | Maurizio Rebaudengo,
Matteo Sonza Reorda:
GALLO: a genetic algorithm for floorplan area optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 943-951 (1996) |
| 24 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 991-1000 (1996) |
| 1995 |
|---|
| 23 | | P. P. Delsanto,
S. Biancotto,
M. Scalerandi,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
Exploiting massively parallel architectures for the solution of diffusion and propagation problems.
HPCN Europe 1995: 1-6 |
| 22 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Enzo Veiluva:
A PVM tool for automatic test generation on parallel and distributed systems.
HPCN Europe 1995: 39-44 |
| 21 | | Stefano Barbagallo,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Testing a Switching Memory in a Telcommunication System.
ITC 1995: 947-956 |
| 20 | | Silvano Gai,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
An improved data parallel algorithm for Boolean function manipulation using BDDs.
PDP 1995: 33-41 |
| 19 | | Fulvio Corno,
Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Enzo Veiluva:
A portable ATPG tool for parallel and distributed systems.
VTS 1995: 29-34 |
| 18 | | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda,
Uwe Gläser,
Heinrich Theodor Vierhaus:
Improving topological ATPG with symbolic techniques.
VTS 1995: 338-343 |
| 17 | | Paolo Camurati,
Paolo Prinetto,
Matteo Sonza Reorda,
Stefano Barbagallo,
Andrea Burri,
Davide Medina:
Industrial BIST of Embedded RAMs.
IEEE Design & Test of Computers 12(3): 86-95 (1995) |
| 1994 |
|---|
| 16 | | Silvano Gai,
Pier Luca Montessoro,
Matteo Sonza Reorda:
TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits.
EDAC-ETC-EUROASIC 1994: 46-50 |
| 15 | | Paolo Prinetto,
Fulvio Corno,
Matteo Sonza Reorda:
An experimental analysis of the effectiveness of the circular self-test path technique.
EURO-DAC 1994: 246-251 |
| 14 | | Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda,
Enzo Veiluva:
GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits.
ICTAI 1994: 411-417 |
| 13 | | Paolo Prinetto,
Maurizio Rebaudengo,
Matteo Sonza Reorda:
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms.
ITC 1994: 240-249 |
| 12 | | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Making the Circular Self-Test Path Technique Effective for Real Circuits.
ITC 1994: 949-957 |
| 11 | | Matteo Sonza Reorda,
Maurizio Rebaudengo:
A Genetic Algorithm for Floorplan Area Optimization.
International Conference on Evolutionary Computation 1994: 93-96 |
| 1993 |
|---|
| 10 | | Gianpiero Cabodi,
Paolo Camurati,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
An approach to sequential circuit diagnosis based on formal verification techniques.
J. Electronic Testing 4(1): 11-17 (1993) |
| 9 | | Gianpiero Balboni,
Gianpiero Cabodi,
Silvano Gai,
Matteo Sonza Reorda:
A Parallel System for Test Pattern Generation.
Parallel Computing 19(2): 177-185 (1993) |
| 1992 |
|---|
| 8 | | Gianpiero Cabodi,
Paolo Camurati,
Fulvio Corno,
Silvano Gai,
Paolo Prinetto,
Matteo Sonza Reorda:
A New Model for Improving symbolic Product Machine Traversal.
DAC 1992: 614-619 |
| 7 | | Gianpiero Cabodi,
Paolo Camurati,
Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda:
Sequential Circuit Diagnosis Based on Formal Verification Techniques.
ITC 1992: 187-196 |
| 1991 |
|---|
| 6 | | Gianpiero Cabodi,
Silvano Gai,
Matteo Sonza Reorda:
Fast Differential Fault Simulation by Dynamic Fault Ordering.
ICCD 1991: 60-63 |
| 5 | | Gianpiero Balboni,
Gianpiero Cabodi,
Silvano Gai,
D. Sismondi,
Matteo Sonza Reorda:
A parallel system for test pattern generation.
SPDP 1991: 708-715 |
| 4 | | Gianpiero Cabodi,
Paolo Camurati,
Paolo Prinetto,
Matteo Sonza Reorda:
TPDL: Extended Temporal Profile Description Language.
Softw., Pract. Exper. 21(4): 355-374 (1991) |
| 1990 |
|---|
| 3 | | Paolo Camurati,
M. Gilli,
Paolo Prinetto,
Matteo Sonza Reorda:
The Use of Model Checking in ATPG for Sequential Circuits.
CAV 1990: 86-95 |
| 2 | | Paolo Camurati,
Antonio Lioy,
Paolo Prinetto,
Matteo Sonza Reorda:
Diagnosis oriented test pattern generation.
EURO-DAC 1990: 470-474 |
| 1 | | Paolo Camurati,
Paolo Prinetto,
Matteo Sonza Reorda:
Exact probabilistic testability measures for multi-output circuits.
J. Electronic Testing 1(3): 229-234 (1990) |
