Phillip Restle

Phillip J. Restle

	2009
12		Cliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert: Ispd2009 clock network synthesis contest. ISPD 2009: 149-150
	2007
11		Rex Berridge, Robert M. Averill III, Arnold E. Barish, Michael A. Bowen, Peter J. Camporese, Jack DiLullo, Peter E. Dudley, Joachim Keinert, David W. Lewis, Robert D. Morel, Thomas Rosser, Nicole S. Schwartz, Philip Shephard, Howard H. Smith, Dave Thomas, Phillip J. Restle, John R. Ripley, Stephen L. Runyon, Patrick M. Williams: IBM POWER6 microprocessor physical design and design methodology. IBM Journal of Research and Development 51(6): 685-714 (2007)
	2005
10		Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti: Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI 2005: 38-43
9		Phillip Restle, Kenneth L. Shepard: New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems. ASYNC 2005
	2004
8		Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, Steve Dodson: Design and implementation of the POWER5 microprocessor. DAC 2004: 670-672
	2003
7		Steven C. Chan, Kenneth L. Shepard, Phillip Restle: Design of Resonant Global Clock Distributions. ICCD 2003: 248-253
	2002
6		James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip Restle, Brian A. Zoric, Carl J. Anderson: The circuit and physical design of the POWER4 microprocessor. IBM Journal of Research and Development 46(1): 27-52 (2002)
	2001
5		Phillip Restle: Technical Visualizations in VLSI Design. DAC 2001: 494-499
4		Phillip Restle, Albert E. Ruehli, Steven G. Walker: Multi-GHz interconnect effects in microprocessors. ISPD 2001: 93-97
3		Phillip Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos: Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 877-886 (2001)
	1999
2		Phillip Restle, Albert E. Ruehli, Steven G. Walker: Dealing with Inductance in High-Speed Chip Design. DAC 1999: 904-909
	1998
1		Phillip Restle, Joel R. Phillips, Ibrahim M. Elfadel: Interconnect in high speed designs: problems, methodologies and tools. ICCAD 1998: 4

Coauthor Index

1	Charles J. Alpert	[12]
2	Carl J. Anderson	[6]
3	Robert M. Averill III	[11]
4	Arnold E. Barish	[11]
5	Rex Berridge	[11]
6	Michael A. Bowen	[11]
7	Thomas J. Bucelot	[10]
8	Peter J. Camporese	[11]
9	Steven C. Chan	[7]
10	Sam Chu	[8]
11	Joachim G. Clabes	[6] [8]
12	James Dawson	[8]
13	Jack DiLullo	[8] [11]
14	Steve Dodson	[8]
15	Peter E. Dudley	[11]
16	Ibrahim M. Elfadel	[1]
17	Giovanni Fiorenza	[10]
18	Michael S. Floyd	[8]
19	Joshua Friedrich	[8]
20	Gary Gorman	[8]
21	Michael Goulet	[8]
22	Ronald N. Kalla	[8]
23	John M. Keaty	[6]
24	Joachim Keinert	[11]
25	Charles J. Kircher	[6]
26	Byron Krauter	[6]
27	Mary Yvonne Lanzerotti	[10]
28	Mike Lee	[8]
29	David W. Lewis	[11]
30	Gerald G. Lopez	[10]
31	Joseph McGill	[8]
32	Robert D. Morel	[11]
33	Paul Muench	[8]
34	Gi-Joon Nam	[12]
35	George Papadopoulos	[3]
36	John G. Petrovick	[6]
37	Joel R. Phillips	[1]
38	Donald W. Plass	[8]
39	Larry Powell	[8]
40	John R. Ripley	[11]
41	Thomas Rosser	[11]
42	Albert E. Ruehli	[2] [3] [4]
43	Stephen L. Runyon	[8] [11]
44	Nicole S. Schwartz	[8] [11]
45	Kenneth L. Shepard	[7] [9]
46	Philip Shephard	[11]
47	Balaram Sinharoy	[8]
48	Howard H. Smith	[11]
49	Mark Sweet	[8]
50	Cliff C. N. Sze (Chin Ngai Sze, Cliff N. Sze)	[12]
51	Dave Thomas	[11]
52	James Wagoner	[8]
53	Steven G. Walker	[2] [3] [4]
54	James D. Warnock	[6]
55	Patrick M. Williams	[11]
56	Brian A. Zoric	[6]

Colors in the list of coauthors