Gerd Ritter

	2000
4		Gerd Ritter: Sequential Equivalence Checking by Symbolic Simulation. FMCAD 2000: 423-442
	1999
3		Gerd Ritter, Holger Hinrichsen, Hans Eveking: Formal Verification of Descriptions with Distinct Order of Memory Operations. ASIAN 1999: 308-321
2		Gerd Ritter, Hans Eveking, Holger Hinrichsen: Formal Verification of Designs with Complex Control by Symbolic Simulation. CHARME 1999: 234-249
1		Hans Eveking, Holger Hinrichsen, Gerd Ritter: Automatic Verification of Scheduling Results in High-Level Synthesis. DATE 1999: 59-64

Coauthor Index

1	Hans Eveking	[1] [2] [3]
2	Holger Hinrichsen	[1] [2] [3]