Eric Rotenberg

2007
30	EE	Vimal K. Reddy, Eric Rotenberg: Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. DSN 2007: 307-316
29	EE	Ahmed S. Al-Zawawi, Vimal K. Reddy, Eric Rotenberg, Haitham Akkary: Transparent control independence (TCI). ISCA 2007: 448-459
28	EE	Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Krishnan Sivasubramanian, Eric Rotenberg: ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling. IEEE Trans. Computers 56(2): 147-160 (2007)
2006
27	EE	Vimal K. Reddy, Eric Rotenberg, Sailashri Parthasarathy: Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. ASPLOS 2006: 83-94
26	EE	Vimal K. Reddy, Eric Rotenberg, Ahmed S. Al-Zawawi: Assertion-Based Microarchitecture Design for Improved Reliability. ICCD 2006
25	EE	Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg: FAST: Frequency-aware static timing analysis. ACM Trans. Embedded Comput. Syst. 5(1): 200-224 (2006)
2005
24	EE	Ali El-Haj-Mahmoud, Ahmed S. Al-Zawawi, Aravindh Anantaraman, Eric Rotenberg: Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing. CASES 2005: 213-224
23	EE	Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Rotenberg: Tapping ZettaRAMTM for Low-Power Memory Systems. HPCA 2005: 83-94
2004
22	EE	Ali El-Haj-Mahmoud, Eric Rotenberg: Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. CASES 2004: 2-13
21	EE	Aravindh Anantaraman, Kiran Seth, Eric Rotenberg, Frank Mueller: Enforcing Safety of Real-Time Schedules on Contemporary Processors Using a Virtual Simple Architecture (VISA). RTSS 2004: 114-125
20	EE	Jinson Koppanalil, Yuanyuan Yang, Jianchao Wang, Eric Rotenberg: A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors. IEEE Trans. Computers 53(4): 399-413 (2004)
2003
19	EE	Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg: Slipstream Execution Mode for CMP-Based Multiprocessors. HPCA 2003: 179-190
18	EE	Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller: Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. ISCA 2003: 350-361
17	EE	Kiran Seth, Aravindh Anantaraman, Frank Mueller, Eric Rotenberg: FAST: Frequency-Aware Static Timing Analysis. RTSS 2003: 40-51
16	EE	Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte: Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embedded Comput. Syst. 2(3): 347-372 (2003)
2002
15	EE	Jinson Koppanalil, Prakash Ramrakhyani, Sameer Desai, Anu Vaidyanathan, Eric Rotenberg: A case for dynamic pipeline scaling. CASES 2002: 1-8
14	EE	Alvin R. Lebeck, Tong Li, Eric Rotenberg, Jinson Koppanalil, Jaidev P. Patwardhan: A Large, Fast Instruction Window for Tolerating Cache Misses. ISCA 2002: 59-70
2001
13	EE	Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte: Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT 2001: 61-
12	EE	Eric Rotenberg: Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. MICRO 2001: 28-39
2000
11	EE	Karthik Sundaramoorthy, Zachary Purser, Eric Rotenberg: Slipstream Processors: Improving both Performance and Fault Tolerance. ASPLOS 2000: 257-268
10	EE	Zachary Purser, Karthik Sundaramoorthy, Eric Rotenberg: A study of slipstream processors. MICRO 2000: 269-280
9	EE	Eric Rotenberg, James E. Smith: Control Independence in Trace Processors. J. Instruction-Level Parallelism 2: (2000)
1999
8	EE	Eric Rotenberg: AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors. FTCS 1999: 84-91
7	EE	Eric Rotenberg, Quinn Jacobson, James E. Smith: A Study of Control Independence in Superscalar Processors. HPCA 1999: 115-124
6	EE	Eric Rotenberg, James E. Smith: Control Independence in Trace Processors. MICRO 1999: 4-15
5	EE	Eric Rotenberg, Steve Bennett, James E. Smith: A Trace Cache Microarchitecture and Evaluation. IEEE Trans. Computers 48(2): 111-120 (1999)
1997
4	EE	Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, James E. Smith: Trace Processors. MICRO 1997: 138-148
3	EE	Quinn Jacobson, Eric Rotenberg, James E. Smith: Path-Based Next Trace Prediction. MICRO 1997: 14-23
1996
2	EE	Erik Jacobsen, Eric Rotenberg, James E. Smith: Assigning Confidence to Conditional Branch Predictions. MICRO 1996: 142-152
1	EE	Eric Rotenberg, Steve Bennett, James E. Smith: Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. MICRO 1996: 24-35

Coauthor Index

1	Haitham Akkary	[29]
2	Ahmed S. Al-Zawawi	[23] [24] [26] [28] [29]
3	Aravindh Anantaraman	[17] [18] [21] [24] [25]
4	Steve Bennett	[1] [5]
5	Gregory T. Byrd	[19]
6	Thomas M. Conte	[13] [16]
7	Sameer Desai	[15]
8	Ali El-Haj-Mahmoud	[22] [24]
9	Khaled Z. Ibrahim	[19]
10	Erik Jacobsen	[2]
11	Quinn Jacobson	[3] [4] [7]
12	Jinson Koppanalil	[14] [15] [20]
13	Alvin R. Lebeck	[14]
14	Tong Li	[14]
15	Frank Mueller	[17] [18] [21] [25]
16	Sailashri Parthasarathy	[27]
17	Kaustubh Patil	[18]
18	Jaidev P. Patwardhan	[14]
19	Zachary Purser	[10] [11]
20	Prakash Ramrakhyani	[15]
21	Vimal K. Reddy	[26] [27] [29] [30]
22	Yiannakis Sazeides	[4]
23	Kiran Seth	[17] [18] [21] [25]
24	Krishnan Sivasubramanian	[28]
25	James E. Smith	[1] [2] [3] [4] [5] [6] [7] [9]
26	Karthik Sundaramoorthy	[10] [11]
27	Mark C. Toburen	[13] [16]
28	Anu Vaidyanathan	[15]
29	Ravi K. Venkatesan	[23] [28]
30	Jianchao Wang	[20]
31	Yuanyuan Yang	[20]
32	Huiyang Zhou	[13] [16]

Colors in the list of coauthors