Nicholas C. Rumin

	2005
14		Min Ma, Mourad Oulmane, Nicholas C. Rumin: Explicit delay metric for interconnect optimization. ISCAS (3) 2005: 2453-2456
	2001
13		Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin: Delay and current estimation in a CMOS inverter with an RC load. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 80-89 (2001)
	1994
12		Abdolreza Nabavi-Lishi, Nicholas C. Rumin: Inverter-based Models for Current Analysis of CMOS Logic Circuits. ISCAS 1994: 13-16
11		Abdolreza Nabavi-Lishi, Nicholas C. Rumin: Inverter models of CMOS gates for supply current and delay evaluation. IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1271-1279 (1994)
	1993
10		Denis Martin, Nicholas C. Rumin: Delay prediction from resistance-capacitance models of general MOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 997-1003 (1993)
	1992
9		Abdolreza Nabavi-Lishi, Nicholas C. Rumin: Delay and bus current evaluation in CMOS logic circuits. ICCAD 1992: 198-203
8		Michel Dagenais, Serge Gaiotti, Nicholas C. Rumin: Transistor-level estimation of worst-case delays in MOS VLSI circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(3): 384-395 (1992)
7		Eduard Cerny, John P. Hayes, Nicholas C. Rumin: Accuracy of magnitude-class calculations in switch-level modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 11(4): 443-452 (1992)
	1991
6		Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin: A recursive technique for computing delays in series-parallel MOS transistor circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 10(5): 589-595 (1991)
	1989
5		Serge Gaiotti, Michel Dagenais, Nicholas C. Rumin: Worst-case Delay Estimation of Transistor Groups. DAC 1989: 491-495
4		Michel Dagenais, Nicholas C. Rumin: On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches. IEEE Trans. on CAD of Integrated Circuits and Systems 8(3): 268-278 (1989)
	1986
3		Michel Dagenais, Vinod K. Agarwal, Nicholas C. Rumin: McBOOLE: A New Procedure for Exact Logic Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 229-238 (1986)
	1985
2		Michel Dagenais, Vinod K. Agarwal, Nicholas C. Rumin: The McBOOLE logic minimizer. DAC 1985: 667-673
	1984
1		Yvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes: A Design for Machines with Built-In Tolerance to Soft Errors. ITC 1984: 649-659

Coauthor Index

1	Vinod K. Agarwal	[1] [2] [3]
2	Jean Paul Caisso	[6]
3	Eduard Cerny	[6] [7]
4	Michel Dagenais	[2] [3] [4] [5] [8]
5	Serge Gaiotti	[5] [8]
6	Mohamed Hafed	[13]
7	Jeremiah F. Hayes	[1]
8	John P. Hayes	[7]
9	Min Ma	[14]
10	Denis Martin	[10]
11	Abdolreza Nabavi-Lishi	[9] [11] [12]
12	Mourad Oulmane	[13] [14]
13	Yvon Savaria	[1]

Colors in the list of coauthors