Rob A. Rutenbar

	2011
120		Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Rob A. Rutenbar: Toward efficient spatial variation decomposition via sparse regression. ICCAD 2011: 162-169
119		Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton: Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 30(12): 1814-1827 (2011)
	2010
118		Wangyang Zhang, Xin Li, Rob A. Rutenbar: Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference. DAC 2010: 262-267
117		Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar: Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation. ICCAD 2010: 47-54
116		Rob A. Rutenbar: Analog layout synthesis: what's missing? ISPD 2010: 43
115		Amith Singhee, Rob A. Rutenbar: Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1763-1776 (2010)
114		Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun: Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs. IEEE Trans. on CAD of Integrated Circuits and Systems 29(12): 1908-1920 (2010)
	2009
113		Amith Singhee, Rob A. Rutenbar: Novel Algorithms for Fast Statistical Analysis of Scaled Circuits Springer 2009: 1-173
112		Patrick Groeneveld, Rob A. Rutenbar, Jed W. Pitera, Erik C. Carlson, Jinsong Chen: Oil fields, hedge funds, and drugs. DAC 2009: 416-417
111		Edward C. Lin, Rob A. Rutenbar: A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer. FPGA 2009: 83-92
110		Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton: Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. ICCAD 2009: 433-440
109		Kai Yu, Rob A. Rutenbar: Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis. INTERSPEECH 2009: 1923-1926
108		Amith Singhee, Rob A. Rutenbar: Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design. IEEE Trans. on CAD of Integrated Circuits and Systems 28(8): 1176-1189 (2009)
	2008
107		Andreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman: Verifying really complex systems: on earth and beyond. DAC 2008: 552-553
106		Amith Singhee, Sonia Singhal, Rob A. Rutenbar: Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. DATE 2008: 856-861
105		Amith Singhee, Sonia Singhal, Rob A. Rutenbar: Practical, fast Monte Carlo statistical static timing analysis: why and how. ICCAD 2008: 190-195
104		Patrick J. Bourke, Rob A. Rutenbar: A low-power hardware search architecture for speech recognition. INTERSPEECH 2008: 2102-2105
103		Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar: Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. VLSI Design 2008: 131-136
102		Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar: Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2317-2330 (2008)
	2007
101		Rob A. Rutenbar: Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains. ASP-DAC 2007
100		Amith Singhee, Rob A. Rutenbar: Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. DAC 2007: 256-261
99		Amith Singhee, Rob A. Rutenbar: Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. DATE 2007: 1379-1384
98		Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen: A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. FPGA 2007: 60-68
97		Kai Yu, Rob A. Rutenbar: Generating small, accurate acoustic models with a modified Bayesian information criterion. INTERSPEECH 2007: 2109-2112
96		Zhong Xiu, Rob A. Rutenbar: Mixed-size placement with fixed macrocells using grid-warping. ISPD 2007: 103-110
95		Amith Singhee, Rob A. Rutenbar: From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis. ISQED 2007: 685-692
94		Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee: Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters CoRR abs/0710.4722: (2007)
93		James D. Ma, Rob A. Rutenbar: Interval-Valued Reduced-Order Statistical Interconnect Modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1602-1613 (2007)
	2006
92		Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar: Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools. DAC 2006: 167-172
91		Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar: Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. DAC 2006: 31-36
90		Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar: Verifying analog oscillator circuits using forward/backward abstraction refinement. DATE 2006: 257-262
89		Rob A. Rutenbar: Design automation for analog: the next generation of tool challenges. ICCAD 2006: 458-460
88		Saurabh K. Tiwary, Rob A. Rutenbar: Faster, parametric trajectory-based macromodels via localized linear reductions. ICCAD 2006: 876-883
87		Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen: Moving speech recognition from software to silicon: the in silico vox project. INTERSPEECH 2006
86		Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar, Oded Maler: Time Domain Verification of Oscillator Circuit Properties. Electr. Notes Theor. Comput. Sci. 153(3): 9-22 (2006)
85		James D. Ma, Rob A. Rutenbar: Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 710-724 (2006)
	2005
84		Saurabh K. Tiwary, Rob A. Rutenbar: Scalable trajectory methods for on-demand analog macromodel extraction. DAC 2005: 403-408
83		Zhong Xiu, Rob A. Rutenbar: Timing-driven placement by grid-warping. DAC 2005: 585-591
82		Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee: Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. DATE 2005: 279-280
81		James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning: Interval-valued statistical modeling of oxide chemical-mechanical polishing. ICCAD 2005: 141-148
80		James D. Z. Ma, Rob A. Rutenbar: Fast interval-valued statistical interconnect modeling and reduction. ISPD 2005: 159-166
79		Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov: Early research experience with OpenAccess gear: an open source development environment for physical design. ISPD 2005: 94-100
	2004
78		Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley: A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. DAC 2004: 155-158
77		Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar: Large-scale placement by grid-warping. DAC 2004: 351-356
76		Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Y. Meng, Ernesto Perea, Robert Pitts, Charles Sodini, Jim Wieser: Will Moore's Law rule in the land of analog? DAC 2004: 633
75		Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar: Towards formal verification of analog designs. ICCAD 2004: 210-217
74		James D. Ma, Rob A. Rutenbar: Interval-valued reduced order statistical interconnect modeling. ICCAD 2004: 460-467
73		Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu: Static statistical timing analysis for latch-based pipeline designs. ICCAD 2004: 468-472
72		Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar: A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. IEEE Trans. Computers 53(6): 688-696 (2004)
	2003
71		Rob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Y. Meng, Reza Rofougaran, James Spoto: Mixed signals on mixed-signal: the right next technology. DAC 2003: 278-279
70		Claire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen: Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. DAC 2003: 496-501
69		Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen: Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. ICCAD 2003: 275-282
68		Hui Xu, Rob A. Rutenbar, Karem A. Sakallah: sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 814-820 (2003)
	2002
67		Hongzhou Liu, Amith Singhee, Rob A. Rutenbar, L. Richard Carley: Remembrance of circuits past: macromodeling by data mining in large analog design spaces. DAC 2002: 437-442
66		Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. FPL 2002: 360-369
65		Hui Xu, Rob A. Rutenbar, Karem A. Sakallah: sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing. ISPD 2002: 182-187
64		Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar: Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform. EURASIP J. Adv. Sig. Proc. 2002(9): 879-892 (2002)
63		Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: A new FPGA detailed routing approach via search-based Booleansatisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 674-684 (2002)
	2001
62		Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen: Panel: (When) Will FPGAs Kill ASICs? DAC 2001: 321-322
61		Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: A boolean satisfiability-based incremental rerouting approach with application to FPGAs. DATE 2001: 560-565
60		Rob A. Rutenbar: Synthesis for Industrial-Scale Analog Intellectual Property. Evolvable Hardware 2001: 3-6
59		Michael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar, L. Richard Carley: ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits. ICCAD 2001: 350-357
58		Prakash Gopalakrishnan, Rob A. Rutenbar: Direct Transistor-Level Layout for Digital Blocks. ICCAD 2001: 577-
57		Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni: Automatic Hierarchical Design: Fantasy or Reality? (Panel). ICCAD 2001: 656-
56		Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen: Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. ICCAD 2001
55		Rob A. Rutenbar, L. Richard Carley, Roberto Zafalon, Nicola Dragone: Low-power technology mapping for mixed-swing logic. ISLPED 2001: 291-294
54		Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar: A comparative study of two Boolean formulations of FPGA detailed routing constraints. ISPD 2001: 222-227
53		Rony Kay, Rob A. Rutenbar: Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution. IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 672-679 (2001)
	2000
52		Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums: A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC. DAC 2000: 1-6
51		Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy: Survival strategies for mixed-signal systems-on-chip (panel session). DAC 2000: 579-580
50		John M. Cohn, Rob A. Rutenbar, Steve Young, Chris Malachowsky, Luis Aldaz: Case studies: Chip design on the bleeding edge (panel session abstract). DAC 2000: 648
49		Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow: Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). DAC 2000: 85
48		Rony Kay, Rob A. Rutenbar: Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution. ISPD 2000: 61-68
47		Rob A. Rutenbar, John M. Cohn: Layout tools for analog ICs and mixed-signal SoCs: a survey. ISPD 2000: 76-83
46		J. Y. F. Tong, David Nagle, Rob A. Rutenbar: Reducing power by optimizing the necessary precision/range of floating-point arithmetic. IEEE Trans. VLSI Syst. 8(3): 273-286 (2000)
45		Rodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. Richard Carley, James R. Hellums: Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 703-717 (2000)
44		Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar: Efficient handling of operating range and manufacturing linevariations in analog cell synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 825-839 (2000)
	1999
43		Michael Krasnicki, Rodney Phelps, Rob A. Rutenbar, L. Richard Carley: MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells. DAC 1999: 945-950
42		Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. FPGA 1999: 167-175
41		Pascal C. H. Meier, Rob A. Rutenbar, L. Richard Carley: Inverse polarity techniques for high-speed/low-power multipliers. ISLPED 1999: 264-266
40		Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar: Satisfiability-Based Detailed FPGA Routing. VLSI Design 1999: 574-577
39		Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley: Device-level early floorplanning algorithms for RF circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 375-388 (1999)
	1998
38		Mehmet Aktuna, Rob A. Rutenbar, L. Richard Carley: Device-level early floorplanning algorithms for RF circuits. ISPD 1998: 57-64
37		R. Glenn Wood, Rob A. Rutenbar: FPGA routing and routability estimation via Boolean satisfiability. IEEE Trans. VLSI Syst. 6(2): 222-231 (1998)
36		Sudip Nag, Rob A. Rutenbar: Performance-driven simultaneous placement and routing for FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 499-518 (1998)
	1997
35		R. Glenn Wood, Rob A. Rutenbar: FPGA Routing and Routability Estimation via Boolean Satisfiability. FPGA 1997: 119-125
34		Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar: A hierarchical decomposition methodology for multistage clock circuits. ICCAD 1997: 266-273
	1996
33		Bulent Basaran, Rob A. Rutenbar: An O(n) Algorithm for Transistor Stacking with Performance Constraints. DAC 1996: 221-226
32		L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen: Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. DAC 1996: 298-303
31		Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley: Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE Trans. on CAD of Integrated Circuits and Systems 15(3): 273-294 (1996)
	1995
30		Sudip K. Nag, Rob A. Rutenbar: Performance-driven simultaneous place and route for island-style FPGAs. ICCAD 1995: 332-338
29		Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar: Testability-oriented channel routing. VLSI Design 1995: 208-213
28		Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar: Integer programming based topology selection of cell-level analog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 401-412 (1995)
	1994
27		Emil S. Ochotta, Rob A. Rutenbar, L. Richard Carley: ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits. DAC 1994: 24-30
26		Sudip Nag, Rob A. Rutenbar: Performance-Driven Simultaneous Place and Route for Row-Based FPGAs. DAC 1994: 301-307
25		Tamal Mukherjee, L. Richard Carley, Rob A. Rutenbar: Synthesis of manufacturable analog circuits. ICCAD 1994: 586-593
	1993
24		Bulent Basaran, Rob A. Rutenbar, L. Richard Carley: Latchup-aware placement and parasitic-bounded routing of custom analog cells. ICCAD 1993: 415-421
	1992
23		Prabir C. Maulik, L. Richard Carley, Rob A. Rutenbar: A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis. DAC 1992: 698-703
22		Sujoy Mitra, Sudip Nag, Rob A. Rutenbar, L. Richard Carley: System-level routing of mixed-signal ASICs in WREN. ICCAD 1992: 394-399
21		Dorothy E. Setliff, Rob A. Rutenbar: Knowledge Representation and Reasoning in a Software Synthesis Architecture. IEEE Trans. Software Eng. 18(6): 523-533 (1992)
	1991
20		Rajeev Jayaraman, Rob A. Rutenbar: A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. ICCAD 1991: 344-347
19		John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley: Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II. ICCAD 1991: 394-397
18		Dorothy E. Setliff, Rob A. Rutenbar: On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF. IEEE Trans. on CAD of Integrated Circuits and Systems 10(6): 783-801 (1991)
17		Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar: Massively parallel switch-level simulation: a feasibility study. IEEE Trans. on CAD of Integrated Circuits and Systems 10(7): 871-894 (1991)
	1990
16		Erik C. Carlson, Rob A. Rutenbar: Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW. DAC 1990: 253-259
	1989
15		Dorothy E. Setliff, Rob A. Rutenbar: ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software. DAC 1989: 543-548
14		Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar: Massively Parallel Switch-Level Simulation: A Feasibility Study. DAC 1989: 91-97
13		Rob A. Rutenbar: Zen and the Art of Analog Design Automation. IFIP Congress 1989: 911
12		Saul A. Kravitz, Randal E. Bryant, Rob A. Rutenbar: Logic Simulation on Massively Parallel Architectures. ISCA 1989: 336-343
11		Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley: OASYS: a framework for analog circuit synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 8(12): 1247-1266 (1989)
	1988
10		Erik C. Carlson, Rob A. Rutenbar: Mask Verification on the Connection Machine. DAC 1988: 134-140
9		Rob A. Rutenbar, Daniel E. Atkins: Systolic routing hardware: performance evaluation and optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 7(3): 397-410 (1988)
	1987
8		Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley: A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. DAC 1987: 42-49
7		Saul A. Kravitz, Rob A. Rutenbar: Placement by Simulated Annealing on a Multiprocessor. IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 534-549 (1987)
6		Erik C. Carlson, Rob A. Rutenbar: A Scanline Data Structure Processor for VLSI Geometry Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 780-794 (1987)
	1986
5		Saul A. Kravitz, Rob A. Rutenbar: Multiprocessor-based placement by simulated annealing. DAC 1986: 567-573
	1985
4		Rob A. Rutenbar: Future directions for DA machine research (panel session). DAC 1985: 496-497
	1984
3		Rob A. Rutenbar, Trevor N. Mudge, Daniel E. Atkins: A Class of Cellular Architectures to Support Physical Design Automation. IEEE Trans. on CAD of Integrated Circuits and Systems 3(4): 264-278 (1984)
	1982
2		Trevor N. Mudge, Rob A. Rutenbar, Robert M. Lougheed, Daniel E. Atkins: Cellular image processing techniques for VLSI circuit layout validation and routing. DAC 1982: 537-543
	1981
1		Rob A. Rutenbar, Y. E. Park: Case study of a VLSI design project: A simple inner product machine. IEEE Symposium on Computer Arithmetic 1981: 184-189

Coauthor Index

1	Emrah Acar	[117] [119]
2	Mehmet Aktuna	[38] [39]
3	Christoph Albrecht	[79]
4	Luis Aldaz	[50]
5	Fadi A. Aloul	[54] [72]
6	Daniel E. Atkins	[2] [3] [9]
7	Karthik Balakrishnan	[120]
8	Max Baron	[62]
9	Bulent Basaran	[24] [33]
10	R. D. (Shawn) Blanton (Ronald D. Blanton)	[110] [119]
11	Anthony R. Bonaccio	[76]
12	Duane S. Boning	[81] [120]
13	Anjan Bose	[107]
14	Patrick J. Bourke	[104]
15	Randal E. Bryant	[12] [14] [17]
16	Benton H. Calhoun	[103] [114]
17	L. Richard Carley	[8] [11] [19] [22] [23] [24] [25] [27] [28] [31] [32] [38] [39] [41] [43] [44] [45] [52] [55] [59] [67] [78]
18	Erik C. Carlson	[6] [10] [16] [112]
19	Henry Chang	[51]
20	Dong Chen	[82] [94]
21	Jinsong Chen	[112]
22	Tsuhan Chen	[64] [69] [70] [87] [98]
23	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[73]
24	Yu-Tsun Chien	[82] [94]
25	Philip Chong	[79]
26	Stephen Y. Chow	[49]
27	John M. Cohn	[19] [47] [50]
28	David E. Corman	[107]
29	Olivier Coudert	[57]
30	Thomas Daniel	[62]
31	E. Aykut Dengi	[78]
32	Nicola Dragone	[55]
33	Gary Ellis	[34]
34	Claire Fang Fang	[64] [69] [70] [81] [92] [102]
35	Suzanne M. Fowler	[77]
36	Goran Frehse	[86] [90]
37	David J. Garrod	[19]
38	Georges G. E. Gielen	[32] [51] [56]
39	Prakash Gopalakrishnan	[58]
40	Patrick Groeneveld	[57] [112]
41	Smriti Gupta	[75]
42	David L. Harame	[71]
43	Ramesh Harjani	[8] [11]
44	James R. Hellums	[45] [52] [59]
45	Mark Horowitz	[49]
46	Cheming Hu	[49]
47	Rajeev Jayaraman	[20] [62]
48	Kurt Johnson	[71]
49	Rony Kay	[48] [53]
50	Paul Kempf	[71]
51	Jitendra Khare	[29]
52	Rudolf Koch	[51]
53	Jürgen Koehl	[57]
54	Michael Krasnicki	[43] [45] [52] [59]
55	Saul A. Kravitz	[5] [7] [12] [14] [17]
56	Bruce H. Krogh	[75] [86] [90]
57	Andreas Kuehlmann	[79] [107]
58	Sandip Kundu	[73]
59	Domine Leenaerts (D. M. W. Leenaerts)	[56]
60	Xin Li	[110] [117] [118] [119] [120]
61	Edward C. Lin	[87] [98] [111]
62	Frank Liu	[117] [119]
63	Hongzhou Liu	[67]
64	Jea-Hong Lou	[82] [94]
65	Robert M. Lougheed	[2]
66	Gin-Kou Ma	[82] [94]
67	James D. Ma	[74] [81] [85] [92] [93] [102]
68	James D. Z. Ma	[77] [80]
69	Chris Malachowsky	[50]
70	Oded Maler	[86]
71	U. Maly	[29]
72	Robert M. Manning	[107]
73	Igor L. Markov	[79]
74	Prabir C. Maulik	[23] [28]
75	Mark McClung	[59]
76	Roy McGuffin	[51]
77	Pascal C. H. Meier	[41]
78	Teresa H. Y. Meng	[71] [76]
79	Sujoy Mitra	[22] [29]
80	Trevor N. Mudge	[2] [3]
81	Tamal Mukherjee	[25] [44] [82] [94]
82	K. C. Murphy	[51]
83	Pranab K. Nag	[29]
84	Sudip Nag	[22] [26] [36]
85	Sudip K. Nag	[30]
86	David Nagle	[46]
87	Gi-Joon Nam	[40] [42] [54] [61] [63] [66] [72]
88	Anna Newman	[107]
89	Emil S. Ochotta	[27] [31]
90	Stephan Ohr	[51]
91	Zvi Or-Bach	[62]
92	David A. Papa	[79]
93	Y. E. Park	[1]
94	Ernesto Perea	[76]
95	Scott Peterson	[57]
96	Rodney Phelps	[43] [45] [52] [59]
97	Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage)	[34]
98	Jed W. Pitera	[112]
99	Robert Pitts	[76]
100	Markus Püschel	[70]
101	Vivek Raghavan	[57]
102	Reza Rofougaran	[71]
103	Ronald A. Rohrer	[78]
104	Jonathan Rose	[62]
105	Karem A. Sakallah	[40] [42] [54] [61] [63] [65] [66] [68] [72]
106	Willy M. C. Sansen	[32]
107	Carl Sechen	[62]
108	Dorothy E. Setliff	[15] [18] [21]
109	Sonia Singhal	[105] [106]
110	Amith Singhee	[67] [92] [95] [99] [100] [102] [103] [105] [106] [108] [113] [114] [115]
111	Charles Sodini	[76]
112	Naresh Soni	[57]
113	James Spoto	[71]
114	Pragati K. Tiwary	[91]
115	Saurabh K. Tiwary	[84] [88] [91]
116	J. Y. F. Tong	[46]
117	Jiajing Wang	[103] [114]
118	Li-C. Wang	[73]
119	Jim Wieser	[76]
120	R. Glenn Wood	[35] [37]
121	Xiaolin Xie	[81]
122	Zhong Xiu	[77] [79] [83] [96]
123	Hui Xu	[65] [68]
124	Steve Young	[50]
125	Kai Yu	[87] [97] [98] [109]
126	Roberto Zafalon	[55]
127	Gang Zhang	[78]
128	Wangyang Zhang	[117] [118] [119] [120]

Colors in the list of coauthors

Last update Fri May 25 01:42:58 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page