 | 2004 |
|---|
| 4 |       | Magesh Sadasivam,
Sangjin Hong:
Dynamically reconfigurable architecture for high-throughput processing of data centric applications.
FPGA 2004: 254 |
| 3 |  | Sangjin Hong,
Shu-Shin Chin,
Magesh Sadasivam:
Glitching power reduction through supply voltage adaptation mechanism for low power array structure design.
ISCAS (2) 2004: 733-736 |
| 2 | | Magesh Sadasivam,
Sangjin Hong:
Autonomous Buffer Controller Design for Concurrent Execution in Block Level Pipelined Dataflow.
ISVLSI 2004: 303-304 |
| 2003 |
|---|
| 1 | | Magesh Sadasivam,
Sangjin Hong:
Application Specific Coarse-Grained FPGA for Processing Element in Real-Time Parallel Particle Filters.
IWSOC 2003: 116-119 |
