Saeed Safari

	2009
15		Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram: Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips. VLSI Design 2009: 151-156
14		Amir-Mohammad Rahmani, I. Kamali, Pejman Lotfi-Kamran, Ali Afzali-Kusha, Saeed Safari: Negative Exponential Distribution Traffic Pattern for Power/Performance Analysis of Network on Chips. VLSI Design 2009: 157-162
	2008
13		Amin Farmahini Farahani, Seid Mehdi Fakhraie, Saeed Safari: Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence. DATE 2008: 1340-1345
12		Saeed Safari: Co-evolutionary reliability-oriented high-level synthesis. ISCAS 2008: 2026-2029
11		Fatemeh Kashfi, Sied Mehdi Fakhraie, Saeed Safari: A 65nm 10GHz pipelined MAC structure. ISCAS 2008: 460-463
	2007
10		Amin Farmahini Farahani, Mehdi Kamal, Seid Mehdi Fakhraie, Saeed Safari: HW/SW partitioning using discrete particle swarm. ACM Great Lakes Symposium on VLSI 2007: 359-364
9		Soheil Aminzadeh, Saeed Safari: Co-evolutionary high-level test synthesis. ACM Great Lakes Symposium on VLSI 2007: 67-72
8		Mohammad Hossein Neishaburi, Masoud Daneshtalab, Mohammad Reza Kakoee, Saeed Safari: Improving Robustness of Real-Time Operating Systems (RTOS) Services Related to Soft-Errors. AICCSA 2007: 528-534
7		Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services. DDECS 2007: 247-250
6		Mojtaba Valinataj, Saeed Safari: Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction. DFT 2007: 188-196
5		Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi: On-Chip Verification of NoCs Using Assertion Processors. DSD 2007: 535-538
	2006
4		MohammadReza EffatParvar, Karim Faez, Mehdi EffatParvar, Mehdi Zarei, Saeed Safari: An Intelligent MLFQ Scheduling Algorithm (IMLFQ) with Fault Tolerant Mechanism. ISDA (3) 2006: 80-85
3		Saeed Safari, Amir-Hossein Jahangir, Hadi Esmaeilzadeh: A parameterized graph-based framework for high-level test synthesis. Integration 39(4): 363-381 (2006)
	2003
2		Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir: Testability Improvement During High-Level Synthesis. Asian Test Symposium 2003: 505
1		Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir: A novel improvement technique for high-level test synthesis. ISCAS (5) 2003: 609-612

Coauthor Index

1	Ali Afzali-Kusha	[14] [15]
2	Soheil Aminzadeh	[9]
3	Masoud Daneshtalab	[5] [7] [8] [15]
4	Mehdi EffatParvar	[4]
5	MohammadReza EffatParvar	[4]
6	Hadi Esmaeilzadeh	[1] [2] [3]
7	Karim Faez	[4]
8	Sied Mehdi Fakhraie (Seid Mehdi Fakhraie)	[10] [11] [13]
9	Amin Farmahini Farahani	[10] [13]
10	Amir-Hossein Jahangir	[1] [2] [3]
11	Mohammad Reza Kakoee	[5] [7] [8]
12	Mehdi Kamal	[10]
13	I. Kamali	[14]
14	Fatemeh Kashfi	[11]
15	Pejman Lotfi-Kamran	[14]
16	Zainalabedin Navabi	[5] [7]
17	Mohammad Hossein Neishaburi	[5] [7] [8]
18	Massoud Pedram	[15]
19	Amir-Mohammad Rahmani	[14] [15]
20	Mojtaba Valinataj	[6]
21	Mehdi Zarei	[4]

Colors in the list of coauthors