C. Safina

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1992

2 Régis Leveugle, C. Safina: Generation of optimized datapaths: bit-slice versus standard cells. Synthesis for Control Dominated Circuits 1992: 153-166

1 C. Safina, Régis Leveugle: Clocking scheme selection for circuits made up of a controller and a datapath. Synthesis for Control Dominated Circuits 1992: 293-308

	1992
2		Régis Leveugle, C. Safina: Generation of optimized datapaths: bit-slice versus standard cells. Synthesis for Control Dominated Circuits 1992: 153-166
1		C. Safina, Régis Leveugle: Clocking scheme selection for circuits made up of a controller and a datapath. Synthesis for Control Dominated Circuits 1992: 293-308

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