Zoran A. Salcic

Zoran Salcic

	2009
37		Roopak Sinha, Partha S. Roop, Samik Basu, Zoran Salcic: Multi-clock Soc design using protocol conversion. DATE 2009: 123-128
36		Yuan He, Morteza Biglari-Abhari, Zoran A. Salcic: Rapid Energy Estimation for Embedded Soft-core Microprocessors. ESA 2009: 133-139
35		Husnain Naqvi, Stevan M. Berber, Zoran Salcic: Performance analysis of collaborative communication in the presence of phase errors and AWGN in wireless sensor networks. IWCMC 2009: 394-398
34		Avinash Malik, Zoran A. Salcic, Alain Girault, Adam Walker, Sung Chul Lee: A customizable multiprocessor for Globally Asynchronous Locally Synchronous execution. JTRES 2009: 120-129
33		Avinash Malik, Zoran A. Salcic, Partha S. Roop: SystemJ compilation using the tandem virtual machine approach. ACM Trans. Design Autom. Electr. Syst. 14(3): (2009)
32		Simon Yuan, Sidharta Andalam, Li Hsien Yoong, Partha S. Roop, Zoran A. Salcic: STARPro - A new multithreaded direct execution platform for Esterel. Electr. Notes Theor. Comput. Sci. 238(1): 37-55 (2009)
	2007
31		Kevin I-Kai Wang, Waleed H. Abdulla, Zoran A. Salcic: Multi-agent System with Hybrid Intelligence Using Neural Network and Fuzzy Inference Techniques. IEA/AIE 2007: 473-482
30		Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: McCharts and Multiclock FSMs for modeling large scale systems. MEMOCODE 2007: 3-12
29		Kevin I-Kai Wang, Waleed H. Abdulla, Zoran A. Salcic: Multi-agent Software Control System with Hybrid Intelligence for Ubiquitous Intelligent Environments. UIC 2007: 1046-1055
28		Wei-Tsun Sun, Zoran Salcic: Modeling RTOS for Reactive Embedded Systems. VLSI Design 2007: 534-539
27		Zoran Salcic, George G. Coghill, R. Bruce Maunder: A genetic algorithm high-level optimizer for complex datapath and data-flow digital systems. Appl. Soft Comput. 7(3): 979-994 (2007)
	2006
26		Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic: The SystemJ approach to system-level design. MEMOCODE 2006: 149-158
25		Roshan Duraisamy, Zoran A. Salcic, Miguel Morales-Sandoval, Claudia Feregrino Uribe: A Fast Elliptic Curve Based Key Agreement Protocol-on-Chip (PoC) for Securing Networked Embedded Systems. RTCSA 2006: 154-161
24		Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid: A Scheduler Support Unit for Reactive Microprocessors. RTCSA 2006: 368-372
23		Kevin I-Kai Wang, Waleed H. Abdulla, Zoran A. Salcic: Distributed Embedded Intelligence Room with Multi-agent Cooperative Learning. UIC 2006: 147-156
22		Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation. VLSI Design 2006: 461-464
21		Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Modeling Embedded Systems: From SystemC and Esterel to DFCharts. IEEE Design & Test of Computers 23(5): 348-358 (2006)
20		Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari: HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems. Microprocessors and Microsystems 30(2): 72-85 (2006)
	2005
19		Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic: Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005 CSREA Press 2005
18		Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari: REMIC: design of a reactive embedded microprocessor core. ASP-DAC 2005: 977-981
17		Lei Yang, Morteza Biglari-Abhari, Zoran A. Salcic: A Power-Efficient Processor Core for Reactive Embedded Applications. Asia-Pacific Computer Systems Architecture Conference 2005: 131-142
16		Flavius Gruian, Zoran A. Salcic: Designing a Concurrent Hardware Garbage Collector for Small Embedded Systems. Asia-Pacific Computer Systems Architecture Conference 2005: 281-294
15		Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Modelling Heterogeneous Embedded Systems in DFCarts. FDL 2005: 441-453
14		Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: A New Model for Heterogeneous Embedded Systems - What Esterel and SyncCharts Need to Become a Suitable Specification Platform. International Journal of Software Engineering and Knowledge Engineering 15(2): 405-410 (2005)
	2004
13		Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Dayaratne: Towards direct execution of esterel programs on reactive processors. EMSOFT 2004: 240-248
12		Zoran A. Salcic, Partha S. Roop: Customizing Processor Cores to Support Reactivity. ERSA 2004: 194-202
11		Zoran A. Salcic, Partha S. Roop, Dong Hui, Ivan Radojevic: HiDRA: A New Architecture for Heterogeneous Embedded Systems. ESA/VLSI 2004: 164-170
10		Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli: REFLIX: a processor core with native support for control-dominated embedded applications. Microprocessors and Microsystems 28(1): 13-25 (2004)
	2003
9		Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli: A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems. VLSI Design 2003: 189-194
	2002
8		Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli: REFLIX: A Processor Core for Reactive Embedded Applications. FPL 2002: 945-945
7		Zoran Salcic: ISDE - an integrated systems development environment for custom-computing machines implemented in FPLDs. Microprocessors and Microsystems 25(9-10): 427-435 (2002)
	2001
6		Zoran A. Salcic: High-speed customizable fuzzy-logic processor: architecture and implementation. IEEE Transactions on Systems, Man, and Cybernetics, Part A 31(6): 731-737 (2001)
5		Jayanthi Sivaswamy, Zoran A. Salcic, K. L. Ling: A Real-Time Implementation of Nonlinear Unsharp Masking with FPLDs. Real-Time Imaging 7(2): 195-202 (2001)
	1999
4		R. Bruce Maunder, Zoran A. Salcic, George G. Coghill: High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules. FPL 1999: 377-384
3		Zoran A. Salcic, Jayanthi Sivaswamy: IMECO: A Reconfigurable FPGA-based Image Enhancement Co-Processor Framework. Real-Time Imaging 5(6): 385-395 (1999)
	1997
2		R. Bruce Maunder, Zoran A. Salcic, George G. Coghill: FPLD HDL synthesis employing high-level evolutionary algorithm optimisation. FPL 1997: 265-273
	1996
1		Zoran A. Salcic, R. Bruce Maunder: CCSimP - An Instruction-level Custom-Configurable Processor for FPLDs. FPL 1996: 280-289

Coauthor Index

1	Waleed H. Abdulla	[23] [29] [31]
2	Sidharta Andalam	[32]
3	Hamid R. Arabnia	[19]
4	Samik Basu	[37]
5	Jürgen Becker	[19]
6	Stevan M. Berber	[35]
7	Abbas Bigdeli	[8] [9] [10]
8	Morteza Biglari-Abhari	[8] [9] [10] [17] [18] [20] [36]
9	George G. Coghill	[2] [4] [27]
10	M. W. Sajeewa Dayaratne	[13]
11	Roshan Duraisamy	[25]
12	Alain Girault	[34]
13	Flavius Gruian	[16] [24] [26]
14	Yuan He	[36]
15	Dong Hui	[11] [18] [20]
16	Masaharu Imai	[19]
17	Sung Chul Lee	[34]
18	K. L. Ling	[5]
19	Avinash Malik	[33] [34]
20	R. Bruce Maunder	[1] [2] [4] [27]
21	Miguel Morales-Sandoval	[25]
22	Husnain Naqvi	[35]
23	Ivan Radojevic	[11] [14] [15] [21] [22] [26] [30]
24	Partha S. Roop	[8] [9] [10] [11] [12] [13] [14] [15] [18] [20] [21] [22] [24] [26] [30] [32] [33] [37]
25	Roopak Sinha	[37]
26	Jayanthi Sivaswamy	[3] [5]
27	Wei-Tsun Sun	[28]
28	Claudia Feregrino Uribe (Claudia Feregrino)	[25]
29	Alif Wahid	[24]
30	Adam Walker	[34]
31	Kevin I-Kai Wang	[23] [29] [31]
32	Laurence Tianruo Yang	[19]
33	Lei Yang	[17]
34	Li Hsien Yoong	[32]
35	Simon Yuan	[32]

Colors in the list of coauthors