 | 2008 |
|---|
| 8 |       | S. Biswas,
S. Mukhopadhyay,
A. Patra,
D. Sarkar:
Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models.
Journal of Circuits, Systems, and Computers 17(6): 1069-1089 (2008) |
| 2006 |
|---|
| 7 |  | S. Biswas,
S. Mukhopadhyay,
P. Patra,
D. Sarkar:
Concurrent Testing of Digital Circuits for Advanced Fault Models.
DDECS 2006: 204-209 |
| 2005 |
|---|
| 6 | | S. Biswas,
P. Srikanth,
R. Jha,
S. Mukhopadhyay,
A. Patra,
D. Sarkar:
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.
Asian Test Symposium 2005: 88-93 |
| 2002 |
|---|
| 5 | | D. Sarkar:
Register Transfer Operation Analysis during Data Path Verification.
VLSI Design 2002: 172- |
| 1997 |
|---|
| 4 | | M. Hira,
D. Sarkar:
Verification of Tempura specification of sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(4): 362-375 (1997) |
| 1989 |
|---|
| 3 | | D. Sarkar,
S. C. De Sarkar:
Some Inference Rules for Integer Arithmetic for Verification of Flowchart Programs on Integers.
IEEE Trans. Software Eng. 15(1): 1-9 (1989) |
| 2 | | D. Sarkar,
S. C. De Sarkar:
A Set of Inference Rules for Quantified Formula Handling and Array Handling in Verification of Programs Over Integers.
IEEE Trans. Software Eng. 15(11): 1368-1381 (1989) |
| 1 | | D. Sarkar,
S. C. De Sarkar:
A Theorem Prover for Verifying Iterative Programs Over Integers.
IEEE Trans. Software Eng. 15(12): 1550-1566 (1989) |
