 | 2009 |
|---|
| 7 |       | Siavash Bayat Sarmadi,
M. Anwar Hasan:
Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures.
IEEE Trans. Computers 58(11): 1553-1567 (2009) |
| 2007 |
|---|
| 6 | | Siavash Bayat Sarmadi,
M. Anwar Hasan:
Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes.
ASAP 2007: 204-209 |
| 5 | | Siavash Bayat Sarmadi,
M. Anwar Hasan:
Detecting errors in a polynomial basis multiplier using multiple parity bits for both inputs.
ICCD 2007: 368-375 |
| 4 | | Siavash Bayat Sarmadi,
M. Anwar Hasan:
On Concurrent Detection of Errors in Polynomial Basis Multiplication.
IEEE Trans. VLSI Syst. 15(4): 413-426 (2007) |
| 2005 |
|---|
| 3 | | Siavash Bayat Sarmadi,
M. Anwar Hasan:
Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme.
DFT 2005: 102-110 |
| 2003 |
|---|
| 2 | | Ali Reza Ejlali,
Seyed Ghassem Miremadi,
Hamid R. Zarandi,
Ghazanfar Asadi,
Siavash Bayat Sarmadi:
A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation.
DSN 2003: 479- |
| 2002 |
|---|
| 1 | | Siavash Bayat Sarmadi,
Seyed Ghassem Miremadi,
Ghazanfar Asadi,
Ali Reza Ejlali:
Fast Prototyping with Co-operation of Simulation and Emulation.
FPL 2002: 15-25 |
