 | 1993 |
|---|
| 15 |       | Amitava Majumdar,
Sarma Sastry:
Statistical Analysis of Controllability.
VLSI Design 1993: 55-60 |
| 14 |  | Amitava Majumdar,
Sarma Sastry:
Probabilistic characterization of controllability in general homogeneous circuits.
Computer-Aided Design 25(2): 76-93 (1993) |
| 1992 |
|---|
| 13 | | Amitava Majumdar,
Sarma Sastry:
On the Distribution of Fault Coverage and Test length in Random Testing of Combinational Circuits.
DAC 1992: 341-346 |
| 12 | | Yung-Te Lai,
Sarma Sastry:
Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification.
DAC 1992: 608-613 |
| 11 | | Yung-Te Lai,
Sarma Sastry,
Massoud Pedram:
Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and Verification.
ICCD 1992: 452-458 |
| 1991 |
|---|
| 10 | | Sarma Sastry,
Amitava Majumdar:
A Branching Process Model for Observability Analysis of Combinational Circuits.
DAC 1991: 452-457 |
| 9 | | King C. Ho,
Sarma Sastry:
Flexible Transistor Matrix (FTM).
DAC 1991: 475-480 |
| 8 | | Sarma Sastry,
Jen-I Pi:
Estimating the minimum of partitioning and floorplanning problems.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(2): 273-282 (1991) |
| 7 | | Sarma Sastry,
Amitava Majumdar:
Test efficiency analysis of random self-test of sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(3): 390-398 (1991) |
| 1989 |
|---|
| 6 | | Sarma Sastry,
Jen-I Pi:
An Investigation into Statistical Properties of Partitioning and Floorplanning Problems.
DAC 1989: 382-387 |
| 5 | | C. P. Ravikumar,
Sarma Sastry:
Parallel Placement on Hypercube Architecture.
ICPP (3) 1989: 97-101 |
| 1988 |
|---|
| 4 | | C. P. Ravi Kumar,
Sarma Sastry:
Parallel Placement on Reduced Array Architecture.
DAC 1988: 121-127 |
| 3 | | Sarma Sastry,
Melvin A. Breuer:
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(9): 933-946 (1988) |
| 1987 |
|---|
| 2 | | Viktor K. Prasanna,
Sarma Sastry:
A General Purpose VLSI Array for Efficient Signal and Image Processsing.
ICPP 1987: 917-920 |
| 1986 |
|---|
| 1 | | Sarma Sastry,
Alice C. Parker:
Stochastic Models for Wireability Analysis of Gate Arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 5(1): 52-65 (1986) |
