Toshinori Sato

	2009
57		Shingo Watanabe, Masanori Hashimoto, Toshinori Sato: A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED 2009: 401-407
56		Toshinori Sato, Shingo Watanabe: Uncriticality-directed scheduling for tackling variation and power challenges. ISQED 2009: 820-825
55		Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura: Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. IEICE Transactions 92-C(4): 483-491 (2009)
	2008
54		Toshinori Sato, Toshimasa Funaki: Dependability, power, and performance trade-off on a multicore processor. ASP-DAC 2008: 714-719
53		Toshimasa Funaki, Toshinori Sato: Formulating MITF for a Multicore Processor with SEU Tolerance. DSD 2008: 234-241
52		Toshinori Sato, Shingo Watanabe: Instruction Scheduling for Variation-Originated Variable Latencies. ISQED 2008: 361-364
51		Shingo Watanabe, Toshinori Sato: Uncriticality-Directed Low-Power Instruction Scheduling. ISVLSI 2008: 69-74
50		Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato: AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP 2008: 83-88
49		Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato: A Low-Power Instruction Issue Queue for Microprocessors. IEICE Transactions 91-C(4): 400-409 (2008)
48		Toshinori Sato: A Simple Mechanism for Collapsing Instructions under Timing Speculation. IEICE Transactions 91-C(9): 1394-1401 (2008)
	2007
47		Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato: Indirect Tag Search Mechanism for Instruction Window Energy Reduction. CIT 2007: 841-846
46		Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato: Challenges in Evaluations for a Typical-Case Design Methodology. ISQED 2007: 374-379
45		Toshinori Sato, Yuji Kunitake: A Simple Flip-Flop Circuit for Typical-Case Designs for DFM. ISQED 2007: 539-544
44		Toshinori Sato, Yuji Kunitake: Exploiting Input Variations for Energy Reduction. PATMOS 2007: 384-393
43		Toshinori Sato, Toshimasa Funaki: Power-Performance Trade-Off of a Dependable Multicore Processor. PRDC 2007: 268-273
42		Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu: Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism. I. J. Comput. Appl. 14(2): 79-91 (2007)
	2006
41		Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu: Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors. PATMOS 2006: 553-562
40		Toshinori Sato, Akihiro Chiyonobu: Evaluating the Impact of Fault Recovery on Superscalar Processor Performance. PRDC 2006: 369-370
39		Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato: A leakage-energy-reduction technique for cache memories in embedded processors. J. Embedded Computing 2(1): 49-55 (2006)
	2005
38		Toshinori Sato: Exploiting Trivial Computation in Dependable Processors. Computers and Their Applications 2005: 168-173
37		Takamasa Tokunaga, Toshinori Sato: Profiling with Helper Threads. Parallel and Distributed Computing and Networks 2005: 1-6
36		Toshinori Sato, Akihiro Chiyonobu: An Energy-Efficient Clustered Superscalar Processor. IEICE Transactions 88-C(4): 544-551 (2005)
	2004
35		Hidenori Sato, Toshinori Sato: A static and dynamic energy reduction technique for I-cache and BTB in embedded processors. ASP-DAC 2004: 830-833
34		Seiichiro Fujii, Toshinori Sato: Non-uniform Set-Associative Caches for Power-Aware Embedded Processors. EUC 2004: 217-226
33		Masaharu Goto, Toshinori Sato: Leakage Energy Reduction in Register Renaming. ICDCS Workshops 2004: 890-895
32		Akihiro Chiyonobu, Toshinori Sato: Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture. ISICT 2004: 190-195
31		Yuu Tanaka, Toshinori Sato, Takenori Koushiro: The potential in energy efficiency of a speculative chip-multiprocessor. SPAA 2004: 273-274
30		Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato: A leakage-energy-reduction technique for highly-associative caches in embedded systems. SIGARCH Computer Architecture News 32(3): 50-54 (2004)
	2003
29		Asami Tanino, Toshinori Sato: Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation. CAINE 2003: 282-287
28		Toshinori Sato: Exploiting Instruction Redundancy for Transient Fault Tolerance. DFT 2003: 547-554
27		Akihito Sakanaka, Toshinori Sato: Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction. PATMOS 2003: 530-539
26		Takenori Koushiro, Toshinori Sato, Itsujiro Arita: A trace-level value predictor for Contrail processors. SIGARCH Computer Architecture News 31(3): 42-47 (2003)
25		Toshinori Sato, Itsujiro Arita: Combining variable latency pipeline with instruction reuse for execution latency reduction. Systems and Computers in Japan 34(12): 11-21 (2003)
	2002
24		Toshinori Sato, Itsujiro Arita: Simplifying Instruction Issue Logic in Superscalar Processors. DSD 2002: 341-346
23		Toshinori Sato, Itsujiro Arita: Low-Cost Value Predictors Using Frequent Value Locality. ISHPC 2002: 106-119
22		Toshinori Sato, Itsujiro Arita: Reducing Energy Consumption via Low-Cost Value Prediction. PATMOS 2002: 380-389
21		Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita: The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization. PDPTA 2002: 1010-1016
20		Toshinori Sato, Kiichi Sugitani, Akihiko Hamano: Evaluating Influence of Compiler Optimizations on Data Speculation. J. Inf. Sci. Eng. 18(6): 1027-1036 (2002)
19		Toshinori Sato: Evaluating the impact of reissued instructions on data speculative processor performance. Microprocessors and Microsystems 25(9-10): 469-482 (2002)
	2001
18		Toshinori Sato, Itsujiro Arita: Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse. Euro-Par 2001: 428-438
17		Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita: Influence of Compiler Optimizations on Value Prediction. HPCN Europe 2001: 312-321
16		Toshinori Sato, Itsujiro Arita: In Search of Efficient Reliable Processor Design. ICPP 2001: 525-532
15		Toshinori Sato, Itsujiro Arita: Tolerating Transient Faults through an Instruction Reissue Mechanism. ISCA PDCS 2001: 240-247
14		Toshinori Sato, Itsujiro Arita: Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications. PRDC 2001: 225-232
	2000
13		Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu: 300MHz design methodology of VU for emotion synthesis. ASP-DAC 2000: 635-640
12		Toshinori Sato, Itsujiro Arita: Partial Resolution in Data Value Predictors. ICPP 2000: 69-76
11		Toshinori Sato, Itsujiro Arita: Table size reduction for data value predictors by exploiting narrow width values. ICS 2000: 196-205
10		Toshinori Sato, Itsujiro Arita: Comprehensive Evaluation of an Instruction Reissue Mechanism. ISPAN 2000: 78-87
9		Toshinori Sato, Itsujiro Arita: The KIT COSMOS Processor: Introducing CONDOR. PDPTA 2000
8		Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki: Vector Unit Architecture for Emotion Synthesis. IEEE Micro 20(2): 40-47 (2000)
7		Toshinori Sato: Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism. Journal of Systems Architecture 46(13): 1231-1252 (2000)
	1999
6		Toshinori Sato: A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism. EUROMICRO 1999: 1178-1185
5		Toshinori Sato: Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure. Euro-Par 1999: 1281-1290
4		Toshinori Sato: Profile-Based Selection of Load Value and Address Predictors. ISHPC 1999: 17-28
3		Toshinori Sato: A Simulation Study of Combining Load Value and Address Predictors. International Journal of High Speed Computing 10(3): 301-325 (1999)
	1998
2		Toshinori Sato: Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue. EUROMICRO 1998: 10285-10292
	1997
1		Toshinori Sato: Data Dependence Path Reductio with Tunneling Load Instructions. ISHPC 1997: 119-130

Coauthor Index

1	Akira Aono	[13]
2	Itsujiro Arita	[9] [10] [11] [12] [14] [15] [16] [17] [18] [21] [22] [23] [24] [25] [26]
3	Akihiro Chiyonobu	[32] [36] [39] [40] [41] [42] [46] [47] [49]
4	Yukio Endo	[8] [13]
5	Seiichiri Fujii	[39]
6	Seiichiro Fujii	[34]
7	Seiichirou Fujii	[30]
8	Toshimasa Funaki	[41] [42] [43] [53] [54]
9	Masaharu Goto	[33]
10	Akihiko Hamano	[17] [20]
11	Masanori Hashimoto	[57]
12	Masashi Hirano	[8]
13	Nobuhiro Ide	[8] [13]
14	Fujio Ishihara	[8] [13]
15	Tohru Ishihara	[50]
16	Yuriko Ishitobi	[50]
17	Takayuki Kamei	[8] [13]
18	Yusuke Kaneda	[50]
19	Shin'ichi Kawakami	[13]
20	Takenori Koushiro	[26] [31] [41] [42]
21	Atsushi Kunimatsu	[8] [13]
22	Yuji Kunitake	[44] [45] [46] [50] [55]
23	Tadayuki Matsumura	[50]
24	Kazuhiro Mima	[55]
25	Kou Morita	[21]
26	Hiroaki Murakami	[8] [13]
27	Masanori Muroyama	[50]
28	Seiji Norimatsu	[13]
29	Akio Ohba	[8]
30	Masaaki Oka	[8]
31	Toyoshi Okada	[8]
32	Yukio Ootaguro	[13]
33	Yuichiro Oyama	[50]
34	Akihito Sakanaka	[27] [30] [39]
35	Hidenori Sato	[35] [41] [42]
36	Takayoshi Shimazawa	[13]
37	Kiichi Sugitani	[17] [20]
38	Masakazu Suzuoki	[8]
39	Kazuhiko Tachibana	[13]
40	Haruyuki Tago	[8]
41	Hideaki Takeda	[13]
42	Koichiro Tanaka	[46]
43	Yuu Tanaka	[31] [41] [42]
44	Asami Tanino	[29]
45	Takamasa Tokunaga	[37]
46	Shingo Watanabe	[47] [49] [51] [52] [56] [57]
47	Seiichiro Yamaguchi	[50]
48	Toshiyuki Yamamoto	[21]
49	Hiroto Yasuura	[55]
50	Teiji Yutaka	[8]

Colors in the list of coauthors