Yasuo Sato

	2008
15		Hiroshi Takahashi, Yoshinobu Higami, Shuhei Kadoyama, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Post-BIST Fault Diagnosis for Multiple Faults. IEICE Transactions 91-D(3): 771-775 (2008)
	2006
14		Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato: A dynamic test compaction procedure for high-quality path delay testing. ASP-DAC 2006: 348-353
13		Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato: Effective Post-BIST Fault Diagnosis for Multiple Faults. DFT 2006: 401-109
12		Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara: A Statistical Quality Model for Delay Testing. IEICE Transactions 89-C(3): 349-355 (2006)
	2005
11		Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara: Evaluation of the statistical delay quality model. ASP-DAC 2005: 305-310
10		Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato: Path delay test compaction with process variation tolerance. DAC 2005: 845-850
	2002
9		Kazumi Hatayama, Michinobu Nakao, Yasuo Sato: At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium 2002: 292-297
8		Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo: Application of High-Quality Built-In Test to Industrial Designs. ITC 2002: 1003-1012
7		Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura: A Persistent Diagnostic Technique for Unstable Defects. ITC 2002: 242-249
	2001
6		Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato: An Approach to Improve the Resolution of Defect-Based Diagnosis. Asian Test Symposium 2001: 123-
5		Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo: Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium 2001: 244-
4		Yasuo Sato, M. Sato, K. Tsutsumida, Toyohito Ikeya, M. Kawashima: A Practical Logic BIST for ASIC Designs. Asian Test Symposium 2001: 457
3		Yasuo Sato, Msaki Kohno, Toshio Ikeda, Iwao Yamazaki, Masato Hamamoto: An evaluation of defect-oriented test: WELL-controlled low voltage test. ITC 2001: 1059-1067
	2000
2		Yasuo Sato, Toyohito Ikeya, Machinobu Nakao, Takaharu Nagumo: A BIST approach for very deep sub-micron (VDSM) defects. ITC 2000: 283-291
	1991
1		Yasushi Ogawa, Tsutomu Itoh, Yoshio Miki, Tatsuki Ishii, Yasuo Sato, Reiji Toyoshima: Timing- and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design. DAC 1991: 253-258

Coauthor Index

1	Takashi Aikyo	[13] [15]
2	Masayasu Fukunaga	[10] [14]
3	Shuji Hamada	[10] [11] [12] [14]
4	Masato Hamamoto	[3]
5	Kazumi Hatayama	[5] [8] [9]
6	Yoshinobu Higami	[13] [15]
7	Toshio Ikeda	[3] [6] [7]
8	Toyohito Ikeya	[2] [4]
9	Tatsuki Ishii	[1]
10	Tsutomu Itoh	[1]
11	Shuhei Kadoyama	[13] [15]
12	Seiji Kajihara	[10] [11] [12] [14]
13	M. Kawashima	[4]
14	Yoshikazu Kiyoshige	[5] [8]
15	Msaki Kohno	[3]
16	Toshiyuki Maeda	[10] [11] [12] [14]
17	Yoshio Miki	[1]
18	Takaharu Nagumo	[2] [5] [8]
19	Machinobu Nakao	[2]
20	Michinobu Nakao	[5] [8] [9]
21	Koichiro Natsume	[8]
22	Yasushi Ogawa	[1]
23	M. Sato	[4]
24	Hiroshi Takahashi	[13] [15]
25	Masahiro Takakura	[6] [7]
26	Yuzo Takamatsu	[13] [15]
27	Atsuo Takatori	[11] [12]
28	Reiji Toyoshima	[1]
29	K. Tsutsumida	[4]
30	Xiaoqing Wen	[10] [14]
31	Hiroki Yamanaka	[6] [7]
32	Iwao Yamazaki	[3] [6] [7]
33	Koji Yamazaki	[13] [15]

Colors in the list of coauthors