Vikram Saxena Coauthor index DBLP Vis pubzone.org

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DBLP keys2004
5no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPrithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, R. Anderson, J. R. Uribe: Overview of a compiler for synthesizing MATLAB programs onto FPGAs. IEEE Trans. VLSI Syst. 12(3): 312-324 (2004)
2003
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPrithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson: Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. FPGA 2003: 237
2002
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVikram Saxena, Farid N. Najm, Ibrahim N. Hajj: Estimation of state line statistics in sequential circuits. ACM Trans. Design Autom. Electr. Syst. 7(3): 455-473 (2002)
1997
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVikram Saxena, Farid N. Najm, Ibrahim N. Hajj: Monte-Carlo approach for power estimation in sequential circuits. ED&TC 1997: 416-420
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee: Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. VLSI Design 1997: 475-481

Coauthor Index

1R. Anderson [4] [5]
2Debabrata Bagchi [4] [5]
3Prithviraj Banerjee (Prith Banerjee) [1] [4] [5]
4Ibrahim N. Hajj [2] [3]
5Malay Haldar [4] [5]
6Michael S. Hsiao [1]
7Victor Kim [4] [5]
8Dilip Krishnaswamy [1]
9Farid N. Najm [2] [3]
10Anshuman Nayak [4] [5]
11Satrajit Pal [4] [5]
12Steven Parkes [5]
13Janak H. Patel [1]
14Elizabeth M. Rudnick [1]
15Nikhil Tripathi [4] [5]
16J. R. Uribe [4] [5]
17David Zaretsky [5]

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