Michael S. Schlansker

	2007
28		Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi: High-performance ethernet-based communications for future multi-core processors. SC 2007: 37
	2006
27		Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder: Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. MICRO 2006: 235-246
	2005
26		Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker: A Distributed Control Path Architecture for VLIW Processors. IEEE PACT 2005: 197-206
25		Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker: Fast synchronization for chip multiprocessors. SIGARCH Computer Architecture News 33(4): 64-69 (2005)
	2003
24		Michael S. Schlansker: In Memory of Bob Rau. MICRO 2003: 165-168
	2001
23		Shail Aditya, Michael S. Schlansker: ShiftQ: a bufferred interconnect for custom loop accelerators. CASES 2001: 158-167
22		B. Ramakrishna Rau, Michael S. Schlansker: Embedded Computer Architecture and Automation. IEEE Computer 34(4): 75-83 (2001)
21		Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood: Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1355-1371 (2001)
20		Michael S. Schlansker, Chris J. Newburn: Guest Editors' Introduction. J. Instruction-Level Parallelism 3: (2001)
	2000
19		B. Ramakrishna Rau, Michael S. Schlansker: Embedded Computing: New Directions in Architecture and Automation. HiPC 2000: 225-244
18		Michael S. Schlansker, B. Ramakrishna Rau: EPIC: Explicititly Parallel Instruction Computing. IEEE Computer 33(2): 37-45 (2000)
	1999
17		Michael S. Schlansker, Scott A. Mahlke, Richard Johnson: Control CPR: A Branch Height Reduction Optimization for EPIC Architectures. PLDI 1999: 155-168
	1997
16		Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe: Challenges to Combining General-Purpose and Multimedia Processors. IEEE Computer 30(12): 33-37 (1997)
15		Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson: Compilers for Instruction-Level Parallelism. IEEE Computer 30(12): 63-69 (1997)
	1996
14		Richard Johnson, Michael S. Schlansker: Analysis Techniques for Predicated Code. MICRO 1996: 100-113
13		David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker: Global Predicate Analysis and Its Application to Register Allocation. MICRO 1996: 114-125
12		Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker: Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO 1996: 58-67
	1995
11		B. Natarajan, Michael S. Schlansker: Spill-free parallel scheduling of basic blocks. MICRO 1995: 119-124
10		Michael S. Schlansker, Vinod Kathail: Critical path reduction for scalar programs. MICRO 1995: 57-69
	1994
9		Michael S. Schlansker, Vinod Kathail, Sadun Anik: Height reduction of control recurrences for ILP processors. MICRO 1994: 40-51
	1993
8		Michael S. Schlansker, Vinod Kathail: Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. LCPC 1993: 406-429
7		Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker: Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. 11(4): 376-408 (1993)
	1992
6		Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker: Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS 1992: 238-247
5		B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai: Code generation schema for modulo scheduled loops. MICRO 1992: 158-169
4		B. Ramakrishna Rau, M. Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker: Register Allocation for Software Pipelined Loops. PLDI 1992: 283-299
	1990
3		Parthasarathy P. Tirumalai, M. Lee, Michael S. Schlansker: Parallelization of loops with exits on pipelined architectures. SC 1990: 200-212
	1989
2		B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen: The Cydram 5 Stride-Insensitive Memory System. ICPP (1) 1989: 242-246
	1982
1		Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker: Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference 1982: 73-84

Coauthor Index

1	Shail Aditya	[23]
2	Sadun Anik	[9]
3	Nathan L. Binkert	[28]
4	Pradip Bose	[1]
5	Dennis Bradford	[28]
6	Roger A. Bringmann	[7]
7	Brad Calder	[27]
8	Richard J. Carter	[28]
9	Chandra Chekuri	[12]
10	William Y. Chen	[6] [7]
11	Nagabhushan Chitlur	[28]
12	Jean-Francois Collard	[25] [27]
13	Thomas M. Conte	[15] [16]
14	James C. Dehnert	[15]
15	Pradeep K. Dubey	[16]
16	Kemal Ebcioglu	[15]
17	Kevin Fan	[26]
18	Jesse Zhixi Fang	[15]
19	David M. Gillies	[13]
20	Rubén González	[25] [27]
21	Richard E. Hank	[7]
22	Wen-mei W. Hwu	[6] [7]
23	Matthew D. Jennings	[16]
24	Richard Johnson	[12] [13] [14] [17]
25	Norman P. Jouppi	[25] [27] [28]
26	Roy Dz-Ching Ju (Roy Ju, Dz-Ching Ju)	[13]
27	Vinod Kathail	[8] [9] [10]
28	M. Lee	[3] [4]
29	Ruby B. Lee	[16]
30	Scott A. Mahlke	[6] [7] [17] [21] [26]
31	Rajeev Motwani	[12]
32	Jayaram Mudigonda	[28]
33	B. Natarajan	[11] [12]
34	Chris J. Newburn	[20]
35	Erwin Oertli	[28]
36	Alex Peleg	[16]
37	Linda Rankin	[28]
38	Salliah Rathnam	[16]
39	B. Ramakrishna Rau	[1] [2] [4] [5] [6] [7] [12] [18] [19] [22]
40	Rajiv A. Ravindran	[21]
41	Jack Sampson	[25] [27]
42	Robert Schreiber	[21]
43	Timothy Sherwood	[21]
44	Peter Song	[16]
45	Paul M. Stillwell Jr.	[28]
46	Carol L. Thompson	[15]
47	Parthasarathy P. Tirumalai	[3] [4] [5]
48	Andrew Wolfe	[16]
49	David W. L. Yen	[2]
50	Hongtao Zhong	[26]

Colors in the list of coauthors